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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Semi-Empirical RC Circuit Model for Non-Filamentary Bi-Layer OxRAM Devices
(2020-03-01)
Majumdar, Swatilekha
;
Chen, Ying
;
Hudec, Boris
;
Hou, Tuo-Hung
;
Suri, Manan
In this brief, we present a semi-empirical RC-circuit-based compact model for non-filamentary bi-layer oxide-based random access memory (OxRAM) devices. The proposed RC model captures both dc and pulse behaviors of the OxRAM devices. Additionally, the model is also able to reproduce the electrical behavior of these devices on application of arbitrary SET/RESET pulses. The model is verified for three non-filamentary OxRAM devices: Ta/HfO2/Al:TiO2/TiN, TiN/TaO/HfOx/TiON/TiN, and Al/AlO sigma /Ta2O5-x/TaOy/W. Through this model, simulation versus experimental error of less than 10% is achieved.
Recommended Methods to Study Resistive Switching Devices
(2019-01-01)
Lanza, Mario
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Wong, H-S Philip
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Pop, Eric
;
Ielmini, Daniele
;
Strukov, Dimitri
Resistive switching (RS) is an interesting property shown by some materials systems that, especially during the last decade, has gained a lot of interest for the fabrication of electronic devices, with electronic nonvolatile memories being those that have received the most attention. The presence and quality of the RS phenomenon in a materials system can be studied using different prototype cells, performing different experiments, displaying different figures of merit, and developing different computational analyses. Therefore, the real usefulness and impact of the findings presented in each study for the RS technology will be also different. This manuscript describes the most recommendable methodologies for the fabrication, characterization, and simulation of RS devices, as well as the proper methods to display the data obtained. The idea is to help the scientific community to evaluate the real usefulness and impact of an RS study for the development of RS technology.
Bipolar Nonlinear Ni/TiO2/Ni Selector for 1S1R Crossbar Array Applications
(2011-10-01)
Huang, Jiun-Jia
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Tseng, Yi-Ming
;
Hsu, Chung-Wei
;
Hou, Tuo-Hung
;
電子工程學系及電子研究所
A bipolar nonlinear selector to suppress the sneak current in the crossbar array has been fabricated using a simple Ni/TiO2/Ni metal-insulator-metal structure. The highly nonlinear current-voltage characteristics are realized by the Schottky emission over the Ni/TiO2 barriers. The series connection with an HfO2-resistive memory device shows reproducible bipolar resistive switching. The maximum array size with at least 10% read margin is projected to exceed megabits. This letter demonstrates the promise of the compact one selector-one resistor (1S1R) cell structure for high-density crossbar array applications.
3D resistive RAM cell design for high-density storage class memory-a review
(2016-06)
Hudec, Boris
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Hsu, Chung-Wei
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Wang, I-Ting
;
Lai, Wei-Li
;
Chang, Che-Chia
In this article, we comprehensively review recent progress in the ReRAM cell technology for 3D integration focusing on a material/device level. First we briefly mention pioneering work on high-density crossbar ReRAM arrays which paved the way to 3D integration. We discuss the two main proposed 3D integration schemes-3D horizontally stacked ReRAM vs 3D Vertical ReRAM and their respective advantages and disadvantages. We follow with the detailed memory cell design on important work in both areas, utilizing either filamentary or interface-limited switching mechanisms. We also discuss our own contributions on HfO2-based filamentary 3D Vertical ReRAM as well as TaOx/TiO2 bilayer-based self-rectifying 3D Vertical ReRAM. Finally, we summarize the present status and provide an outlook for the nearterm future.
Fully parallel write/read in resistive synaptic array for accelerating on-chip learning
(2015-11-13)
Gao, Ligang
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Wang, I-Ting
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Chen, Pai-Yu
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Vrudhula, Sarma
;
Seo, Jae-Sun
A neuro-inspired computing paradigm beyond the von Neumann architecture is emerging and it generally takes advantage of massive parallelism and is aimed at complex tasks that involve intelligence and learning. The cross-point array architecture with synaptic devices has been proposed for on-chip implementation of the weighted sum and weight update in the learning algorithms. In this work, forming-free, silicon-process-compatible Ta/TaOx/TiO2/Ti synaptic devices are fabricated, in which >200 levels of conductance states could be continuously tuned by identical programming pulses. In order to demonstrate the advantages of parallelism of the cross-point array architecture, a novel fully parallel write scheme is designed and experimentally demonstrated in a small-scale crossbar array to accelerate the weight update in the training process, at a speed that is independent of the array size. Compared to the conventional row-by-row write scheme, it achieves >30x speed-up and >30x improvement in energy efficiency as projected in a large-scale array. If realistic synaptic device characteristics such as device variations are taken into an array-level simulation, the proposed array architecture is able to achieve similar to 95% recognition accuracy of MNIST handwritten digits, which is close to the accuracy achieved by software using the ideal sparse coding algorithm.
Flexible Three-Bit-Per-Cell Resistive Switching Memory Using a-IGZO TFTs
(2013-10-01)
Wu, Shih-Chieh
;
Feng, Hsien-Tsung
;
Yu, Ming-Jiue
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Wang, I-Ting
;
Hou, Tuo-Hung
This letter proposes a novel high bit density nonvolatile memory using a logic compatible flexible amorphous indium-gallium-zinc oxide (a-IGZO) thin-film transistor (TFT) structure fabricated at low temperature. Before electrical forming, the a-IGZO TFT exhibits excellent transistor performance, including an ON/OFF current ratio of 8.8 x 10(6), a steep subthreshold slope of 0.14 V/decade, a threshold voltage of 0.55 V, and a maximum field-effect mobility of 2 cm(2)/Vs. After electrical forming, a three-bit-per-cell resistive switching memory is realized using localized multilevel resistance states at the drain and source bits. Combining dual functionalities to achieve low-cost integration and excellent device characteristics at bending states, the proposed device is promising for future system-on-plastic applications.
Rapid Prediction of RRAM RESET-State Disturb by Ramped Voltage Stress
(2012-04-01)
Luo, Wun-Cheng
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Lin, Kuan-Liang
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Huang, Jiun-Jia
;
Lee, Chung-Lun
;
Hou, Tuo-Hung
This letter proposes a novel technique for predicting with high confidence the disturbance of the resistive-switching random access memory (RRAM) RESET state based on ramped voltage stress. The technique yields statistical distributions and voltage acceleration parameters equivalent to those of a conventional constant voltage method. Several ramp rates and acceleration models were validated for the accuracy regarding conversion between the two methods. The proposed method not only reduces the time and cost of reliability analysis but also provides a quantitative link between disturbance properties and the widely available RRAM data measured by a linear voltage ramp. Additionally, the non-Poisson area scaling supports the localized filament model.

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