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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Hsieh, Chen-YuSubject: search.filters.subject.tunneling

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Now showing 1 - 4 of 4
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    Measurement of channel stress using gate direct tunneling current in uniaxially stressed nMOSFETs
    (2007-09-01)
    Hsieh, Chen-Yu
    ;
    Chen, Ming-Jer
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We measure the conduction-band electron direct tunneling current through the 1.27-nm gate oxide of nMOSFETs transistors that undergo longitudinal stress via a layout technique. With known process parameters and published deformation potential constants as input, fitting of the measured direct tunneling current versus gate voltage leads to the channel stress of around 0, -100, and -300 MPa for a gate-to-trench isolation spacing of 2.4, 0.495, and 0.21 mu m, respectively. To examine the accuracy of the method, a link with the mobility and threshold voltage measurements on the same device is conducted. The resulting piezoresistance coefficient and band offset are in good agreement with the literature values. The layout technique used is validated as well.
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    Electrical measurement of local stress and lateral diffusion near Source/Drain extension corner of uniaxially stressed n-MOSFETs
    (2008-03-01)
    Hsieh, Chen-Yu
    ;
    Chen, Ming-Jer
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    -On a 1.27-nm gate oxide n-MOSFET that undergoes longitudinal stress via a layout technique, subthreshold current is measured as a function of the gate edge to shallow-trench isolation (STI) spacing and is transformed via bandgap shift into the source/drain extension corner stress. The extracted local stress is quantitatively comparable with those of the channel as created by the gate direct tunneling measurement in inversion, the mobility measurement, and the threshold voltage measurement. In addition, its dependencies on the gate edge to STI spacing confirm the validity of the layout technique in controlling the corner or channel stress. The gate edge direct tunneling (EDT) measurement in accumulation straightforwardly leads to the quantified gate-to-source/drain-extension overlap length. Particularly, a retarded diffusion length of 1.1 nm for a stress change of -320 MPa and the resulting strain-induced activation energy both are in satisfactory agreement with those of the process simulation. A physically oriented analytic model is, therefore, reached, expressing the lateral diffusion as a function of the corner stress.
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    Distinguishing Between STI Stress and Delta Width in Gate Direct Tunneling Current of Narrow n-MOSFETs
    (2009-05-01)
    Hsieh, Chen-Yu
    ;
    Lin, Yi-Tang
    ;
    Chen, Ming-Jer
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Direct tunneling current across a 1.27-nm-thick gate oxide of n-MOSFETs under STI compressive stress is measured in a wide range of the drawn gate width W (= 0.11, 0.24, 0.6, 1.0 and 10 mu m). The apparent gate current per unit width exhibits an increasing trend with decreasing W. In this narrowing direction, two fundamentally different effects are encountered: one of the delta width (Delta W) near the STI edge, and the other of the enhanced STI stress in the channel. To distinguish between the two effects, a new analytical width-dependent direct tunneling model is developed and applied. Reasonable agreement with data is achieved. The resulting delta width effect is found to dominate over the stress effect in narrow devices, while for the wide ones, they are comparable. The extracted Delta W (similar to 63 nm) and the underlying channel stress (with the uncertainties identified) straightforwardly produce a good fitting of the drain current variation counterpart. Specifically, it is justified that the delta width and STI stress are cooperative in constituting gate current variation, but both have opposite effects on the drain current one.
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    Enhanced Hole Gate Direct Tunneling Current in Process-Induced Uniaxial Compressive Stress p-MOSFETs
    (2009-08-01)
    Hsu, Chih-Yu
    ;
    Lee, Chien-Chih
    ;
    Lin, Yi-Tang
    ;
    Hsieh, Chen-Yu
    ;
    Chen, Ming-Jer
    On a nominally 1.27-nm-thick gate oxide p-MOSFET with shallow trench isolation (STI) longitudinal compressive mechanical stress, hole gate direct tunneling current in inversion is measured across the wafer. The resulting average gate current exhibits an increasing trend with STI compressive stress. However, this is exactly contrary to the currently recognized trend: hole gate direct tunneling current decreases with externally applied compressive stress, which is due to the strain-altered valence-band splitting. To determine the mechanisms responsible, a quantum strain simulator is established, and its validity is confirmed. The simulator then systematically leads us to the finding of the origin: a reduction in the physical gate oxide thickness, with the accuracy identified down to 0.001 nm, occurs under the influence of the STI compressive stress. The strain-retarded oxide growth rate can significantly enhance hole direct tunneling and thereby reverse the conventional trend due to the strain-altered valence-band splitting.