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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Hsieh, Yi-BinHas files: Yes

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    A high performance spread spectrum clock generator using two-point modulation scheme
    (2008-06-01)
    Kao, Yao-Huang
    ;
    Hsieh, Yi-Bin
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved with lower order Sigma Delta modulator and can simultaneously optimize the jitter and the modulation profile. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSCG has been fabricated in a 0.35 mu m CMOS process. The clock of 400 MHz with center spread ratios of 1.25% and 2.5% are verified. The peak EMI reduction is 19.73 dB for the case of 2.5%. The size of chip area is 0.90 X 0.89 mm(2).
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    Item type:Item,
    A fully integrated spread-spectrum clock generator by using direct VCO modulation
    (2008-08-01)
    Hsieh, Yi-Bin
    ;
    Kao, Yao-Huang
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    A compact architecture for a fully-integrated spread-spectrum clock generator (SSCG) using voltage-controlled oscillator direct modulation is presented in this paper. A dual-path loop filter in the phase-locked loop is employed to reduce the size of the capacitance in the filter with the aid of an extra charge pump and a unity gain amplifier. At the same time, a third-charge pump which generates triangular waves is used to perform the function of a spread-spectrum. The proposed circuit has been fabricated using a 0.35-mu m CMOS single-poly quadruple-metal process. The clock rate from 50 to 480 MHz with a center spread range of between 0.5 % and 2 % are verified and are close to the theoretical analyses. The size of the chip area is 0.82 x 0.8 mm(2) (including the loop filter) and the power consumption was 27.5 mW at 400 MHz. Index Terms-Phase-locked loop (PLL), spread-spectrum clock generator (SSCG).
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    Item type:Item,
    A fully integrated spread spectrum clock generator using two-point delta-sigma modulation
    (2007)
    Hsieh, Yi-Bin
    ;
    Kao, Yao-Huang
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    A new spread spectrum clock generator (SSCG) using two-point delta-sigma modulation is presented in this paper. Not only the divider is varied, but also the voltage controlled oscillator is modulated. This technique can enhance the modulation bandwidth so that the effect of EMI suppression is improved. In addition, the method of two-path is applied to the loop filter to reduce the capacitance value such that the total integration can be achieved. The proposed SSG has been fabricated in a 0.35um CMOS process. The clock of 400MHz with center spread ratios of 1.25% and 2.5% are verified. The size of chip area is 0.90x0.89 mm(2).
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    Item type:Item,
    A Low-Power and High-Precision Spread Spectrum Clock Generator for Serial Advanced Technology Attachment Applications Using Two-Point Modulation
    (2009-05-01)
    Kao, Yao-Huang
    ;
    Hsieh, Yi-Bin
    ;
    傳播研究所
    ;
    Institute of Communication Studies
    A new technique utilizing two-point (TP) modulation for a spread spectrum clock generator (SSCG) for serial advanced technology attachment is presented in which the divider ratio is varied by a digital Sigma Delta modulator, and the voltage-controlled oscillator is modulated analogically. With this technique, the modulation bandwidth is enhanced in order that the modulation profile accuracy and jitter performance caused by the Sigma Delta modulator can be improved at the same time. The order of the Sigma Delta modulator and the loop filter can be reduced to save power and area, while the electromagnetic interference (EMI) suppression still satisfies specifications. The dual-path loop filter (DL) reduces the size of the loop capacitor and enables full integration. The proposed TPDL-SSCG has been fabricated in a 0.18-mu m CMOS process. The size of the chip area is 0.44 x 0.48 mm(2). The circuit produces a clock of 1.5 GHz with a down-modulation ratio of 0.5%, 10.14 dB EMI of reduction, 5.485 ps rms jitter, and 35 ps peak-to-peak jitter. The power consumption, excluding an output buffer, is only 15.3 mW.