學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 7 of 7

Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
(2003-02-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the, base or - substrate of the SCR device, it can be quickly triggered, into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with, general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR, devices can be stacked in ESD protection circuits to avoid the translient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices, can be reduced from 27.4 to 7.8 ns by the substrate-triggering, technique. The substrate-triggered SCR device with a small active area of only 20 mum x 20 mum can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-mum CMOS process.
Latchup-free ESD protection design with complementary substrate-triggered SCR devices
(2003-08-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The turn-on mechanism of silicon-controlled rectifier (SCR) devices is essentially a current triggering event. While a current is applied to the base or substrate of an SCR device, it can be quickly triggered on into its latching state. In this paper, latchup-free electrostatic discharge (ESD) protection circuits which are combined with the substrate-triggered technique and an SCR device, are proposed. A complementary circuit style with the substrate-triggered SCR device is designed to discharge both the pad-to-V-SS and pad-to-V-DD ESD stresses. The novel complementary substrate-triggered SCR devices have the advantages of controllable switching voltage, adjustable holding voltage, faster turn-on speed, and compatible to general CMOS process without extra process modification such as the silicide-blocking mask and ESD implantation. The total holding voltage of the substrate-triggered SCR device can be linearly increased by adding the stacked diode string to avoid the transient-induced latchup issue in the ESD protection circuits. The on-chip ESD protection circuits designed with the proposed complementary substrate-triggered SCR devices and stacked diode string for the input/output pad and power pad have been successfully verified in a 0.25-mum salicided CMOS process with the human body model (machine model) ESD level of similar to7.25 kV (500 V) in a small layout area.
SCR device with double-triggered technique for on-chip ESD protection in sub-quarter-micron silicided CMOS processes
(2003-09-01)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
Turn-on efficiency is the main concern for silicon-controlled rectifier (SCR) devices used as on-chip electrostatic discharge (ESD) protection circuit, especially in deep sub-quarter-micron CMOS processes with much thinner gate oxide. A novel double-triggered technique is proposed to speed up the turn-on speed of SCR devices for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide in sub-quarter-micron CMOS processes. From the experimental results, the switching voltage and turn-on time of such double-triggered SCR (DT_SCR) device has been confirmed to be significantly reduced by this double-triggered technique.
Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
(2003-11-15)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
Turn-on speed is the main concern for on-chip electrostatic discharge (ESD) protection device, especially, in deep submicron complementary metal-oxide semiconductors (CMOS) processes with ultra-thin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device with substrate-triggered technique is proposed to improve the turn-on speed of SCR device for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide. From the experimental results, the switching voltage, turn-on resistance, and turn-on time of substrate-triggered SCR (STSCR) device with dummy-gate structure have been efficiently improved, as compared with the normal SCR with shallow trench isolation (STI) structure.
SCR device fabricated with dummy-gate structure to improve turn-on speed for effective ESD protection in CMOS technology
(2005-05-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Turn-on speed is the main concern for an on-chip electrostatic discharge (ESD) protection device, especially in the nanoscale CMOS processes with ultrathin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device employing a substrate-triggered technique is proposed to improve the turn-on speed of an SCR device for using in an on-chip ESD protection circuit to effectively protect the much thinner gate oxide. The fabrication of the proposed SCR device with dummy-gate structure is fully process-compatible with general CMOS process, without using an extra mask layer or adding process steps. From the experimental results in a 0.25-mu m CMOS process with a gate-oxide thickness of similar to 50 angstrom, the switching voltage, turn-on speed, turn-on resistance, and charged-device-model ESD levels of the SCR device with dummy-gate structure have been greatly improved, as compared to the normal SCR with shallow trench isolation structure.
Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
(2005-06-01)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.
Native-NMOS-triggered SCR With faster turn-on speed for effective ESD protection in a 0.13-mu m CMOS process
(2005-09-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In order to quickly discharge the electrostatic discharge (ESD) energy and to efficiently protect the ultrathin gate oxide, a novel native-negative-channel metal oxide semiconductor (NMOS)-triggered silicon-controlled rectifier (NANSCR) is proposed for on-chip ESD protection in a 0.13-mu m complementary metal oxide semiconductor (CMOS) process with a voltage supply of 1.2 V. The proposed NANSCR can be designed for the input, output, and power-rail ESD protection circuits without latchup danger. A new whole-chip ESD protection scheme realized with the proposed NANSCR devices is also demonstrated with the consideration of pin-to-pin ESD stress. From the experimental results, the trigger voltage, holding voltage, turn-on resistance, turn-on speed, and charged-device-model (CDM) ESD level of NANSCR can be greatly improved, as compared with the traditional low-voltage-triggering SCR (LVTSCR). Under transmission line pulsing (TLP) stress, the gate leakage current of the gate monitor device protected by the proposed NANSCR is monitored after each TLP pulse, whereas the gate leakage current is not obviously increased. Therefore, the ultrathin gate oxide of the input stage can be safely protected by the new proposed NANSCR against ESD stress in the nanoscale CMOS technology.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results