<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Hsu, Li-HanSubject: search.filters.subject.packaging

Search Results

Now showing 1 - 3 of 3
  • Thumbnail Image
    Item type:Item,
    Design of Flip-Chip Interconnect Using Epoxy-Based Underfill Up to V-Band Frequencies With Excellent Reliability
    (2010-08-01)
    Hsu, Li-Han
    ;
    Wu, Wei-Cheng
    ;
    Chang, Edward Yi
    ;
    Zirath, Herbert
    ;
    Hu, Yin-Chu
    This study demonstrates a flip-chip interconnect with epoxy-based underfill (epsilon(r) = 3.5 and tan delta = 0.02 at 10 MHz) for packaging applications up to V-band frequencies. To achieve the best interconnect performance, both the matching designs on GaAs chip and Al(2)O(3) substrate were adopted with the underfill effects taken into consideration. The optimized flip-chip interconnect showed excellent performance from dc to 67 GHz with return loss below -20 dB and insertion loss less than 0.6 dB. Furthermore, the dielectric loss induced by the underfill was extracted from measurement and compared with the simulation results. The reliability tests including 85 degrees C/85 % relative humidity test, thermal cycling test, and shear force test were performed. For the first time, the S-parameters measurement was performed to check the flip-chip reliability, and no performance decay was observed after 1000 thermal cycles. Moreover, the mechanical strength was improved about 12 times after the underfill was applied. The results show that the proposed flip-chip architecture has excellent reliability and can be applied for commercial applications.
  • Thumbnail Image
    Item type:Item,
    Design, Fabrication, and Reliability of Low-Cost Flip-Chip-On-Board Package for Commercial Applications up to 50 GHz
    (2012-03-01)
    Hsu, Li-Han
    ;
    Oh, Chee-Way
    ;
    Wu, Wei-Cheng
    ;
    Chang, Edward Yi
    ;
    Zirath, Herbert
    This paper presents a flip-chip-on-board (FCOB) packaging technology using a Rogers RO3210 laminate for microwave applications. Compared to the conventional microwave packaging architecture, the proposed FCOB technology skips one level of the ceramic package and thus results in lower reflections and manufacturing costs. To fulfill the small dimension requirement on printed circuit boards, the coplanar waveguide (CPW) transmission line and flip-chip bump were fabricated on a high-k RO3210 board (epsilon(r) = 10.2) with photolithography and electroplating. The GaAs chip patterned with the CPW line was then flip-chip-mounted onto the RO3210 laminate board. This structure displayed excellent performance from dc to 50 GHz with a return loss S-11 greater than 18 dB and insertion loss S-21 less than 0.5 dB. Meanwhile, the flip-chip bonding of the in-house-fabricated In0.52Al0.As-48/In0.6Ga0.4As metamorphic high-electron-mobility transistor devices on RO3210 also displayed excellent gain performance with a small degradation of 1 dB from dc to 40 GHz, showing the potential of implementing microwave integrated circuits on RO3210. To enhance the mechanical reliability, an epoxy-based underfill was injected into the flip-chip assemblies. Thermal cycling tests were performed to test the interconnect reliability, and the results indicated that the samples passed the thermal cycling test at least up to 600 cycles, showing excellent reliability for commercial applications. To the best of the authors' knowledge, this is the first study that evaluates the use of the RO3210 laminate for microwave flip-chip in open literature.
  • Thumbnail Image
    Item type:Item,
    Design and Fabrication of 0/1-Level RF-Via Interconnect for RF-MEMS Packaging Applications
    (2010-02-01)
    Hsu, Li-Han
    ;
    Wu, Wei-Cheng
    ;
    Chang, Edward Yi
    ;
    Zirath, Herbert
    ;
    Wu, Yun-Chi
    This paper presents the parametric study of RF-via (0-level) and flip-chip bump (1-level) transitions for applications of packaging coplanar RF-MEMS devices. The key parameters were found to be the bumps' and vias' positions and the overlap of the metal pads, which should be carefully considered in the entire two levels of packages. The length of the backside transmission line, determining the MEMS substrate area, showed minor influence on the interconnect performance. With the experimental results, the design rules have been developed and established. The optimized interconnect structure for the two levels of packages demonstrates the return loss beyond 15 dB and the insertion loss within 0.6 dB from dc to 60 GHz.