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學術出版;;Publications

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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Author: search.filters.author.Hsu, SFSubject: search.filters.subject.latchup

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    Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test
    (2005-08-01)
    Ker, MD
    ;
    Hsu, SF
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-mu m CMOS technology.
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    Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
    (2006-02-01)
    Ker, MD
    ;
    Hsu, SF
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against the transient-induced latchup (TLU) under the system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structures and the ring oscillator circuit fabricated in a 0.25-mu m CMOS technology. Some board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products.