<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

Filters

2011 - 20132

Settings

🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Huang, Li-ChunSubject: search.filters.subject.Algorithm

Search Results

Now showing 1 - 2 of 2
  • Thumbnail Image
    Item type:Item,
    An Adaptive, Low-Cost Wear-Leveling Algorithm for Multichannel Solid-State Disks
    (2013-12-01)
    Chang, Li-Pin
    ;
    Chou, Tung-Yang
    ;
    Huang, Li-Chun
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. As flash memory endures only limited program-erase cycles, solid-state disks employ wear-leveling methods to prevent any portions of flash memory from being retired prematurely. Modern solid-state disks must consider wear evenness at both block and channel levels. This study first presents a block-level wear-leveling method whose design has two new ideas. First, the proposed method reuses the intelligence available in flash-translation layers so it does not require any new data structures. Second, it adaptively tunes the threshold of block-level wear leveling according to the runtime write pattern. This study further introduces a new channel-level wear-leveling strategy, because block-level wear leveling is confined to a channel, but realistic workloads do not evenly write all channels. The proposed method swaps logical blocks among channels for achieving an eventually-even state of channel lifetimes. A series of trace-driven simulations show that our wear-leveling method outperforms existing approaches in terms of wear evenness and overhead reduction.
  • Thumbnail Image
    Item type:Item,
    A Low-Cost Wear-Leveling Algorithm for Block-Mapping Solid-State Disks
    (2011)
    Chang, Li-Pin
    ;
    Huang, Li-Chun
    ;
    資訊工程學系
    ;
    Department of Computer Science
    Multilevel flash memory cells double or even triple storage density, producing affordable solid-state disks for end users. However, flash lifetime is becoming a critical issue in the popularity of solid-state disks. Wear-leveling methods can prevent flash-storage devices from prematurely retiring any portions of flash memory. The two practical challenges of wear-leveling design are implementation cost and tuning complexity. This study proposes a new wear-leveling design that features both simplicity and adaptiveness. This design requires no new data structures, but utilizes the intelligence available in sector-translating algorithms. Using an on-line tuning method, this design adaptively tunes itself to reach good balance between wear evenness and overhead. A series of trace-driven simulations show that the proposed design outperforms a competitive existing design in terms of wear evenness and overhead reduction. This study also presents a prototype that proves the feasibility of this wear-leveling design in real solid-state disks.