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Author: search.filters.author.Huang, Shin-PingSubject: search.filters.subject.Stress

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Now showing 1 - 4 of 4
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    Effect of ELA Energy Density on Self-Heating Stress in Low-Temperature Polycrystalline Silicon Thin-Film Transistors
    (2020-08-01)
    Huang, Shin-Ping
    ;
    Chen, Hong-Chih
    ;
    Chen, Po-Hsun
    ;
    Zheng, Yu-Zhe
    ;
    Chu, Ann-Kuo
    The extent of the poly-silicon crystalline protrusion, a result of differences in excimer laser annealing (ELA), affects the performance and reliability of thin-film transistors (TFTs). This study investigates the degradation mechanism of the low-temperature polycrystalline silicon (LTPS) TFT devices with differences in crystalline protrusion under self-heating stress (SHS). Higher ELA energy will induce higher protrusion height in the interface between the poly-silicon and gate insulator (GI). This surface morphology leads to serious charge trapping into the GI layers; in contrast, the smallest degradation after SHS can be seen in the devices with the lowest protrusion height. This indicates that the degradation is caused by the surface morphology between the poly-Si and GI interface. In addition, the COMSOL simulation results confirm that the large electric field in the GI layer appears in the rough surface morphology devices; therefore, choosing the appropriate ELA energy of the poly-Si is beneficial for the applications of the driving TFT in organic light-emitting diode (OLED) display in the manufacturing industry.
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    Enhancement of Mechanical Bending Stress Endurance Using an Organic Trench Structure in Foldable Polycrystalline Silicon TFTs
    (2020-05-01)
    Zheng, Yu-Zhe
    ;
    Huang, Shin-Ping
    ;
    Chen, Po-Hsun
    ;
    Chang, Ting-Chang
    ;
    Tsai, Tsung-Ming
    This letter proposes a new organic trench structure which can enhance the endurance of polycrystalline silicon thin film transistors (TFTs) under mechanical bending stress. It compares conventional structure TFTs to devices with an organic trench to examine reliability after undergoing 100,000 iterations of channel width-axis (100,000'WC) compression at R = 2mm. Due to the low Young's modulus of organic materials, stress while undergoing bending strain is desorbed to the buffer layer, which can lower the overall stress in TFTs. Furthermore, an optimal location and ideal length for such an organic trench is evaluated by mechanical bending simulation.
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    Analysis of Negative Bias Temperature Instability Degradation in p-Type Low-Temperature Polycrystalline Silicon Thin-Film Transistors of Different Grain Sizes
    (2019-11-01)
    Tu, Hong-Yi
    ;
    Tsao, Yu-Ching
    ;
    Tai, Mao-Chou
    ;
    Chang, Ting-Chang
    ;
    Tsai, Yu-Lin
    This letter investigates degradation after negative bias temperature instability (NBTI) stress applied to LTPS TFTs with different polycrystalline-silicon grain sizes. The initial characteristics of the LTPS TFTs are similar regardless of grain size; however, we observed a different degree of degradation after NBTI depending on grain size. In general, after NBTI, both grain boundary traps and interface traps were generated. We found that the degree of NBTI degradation is dominated by the concentration of grain boundary traps, which themselves are a result of the different grain sizes that occur due to excimer laser annealing energy. At initial, dangling bonds in the grain boundaries and at the interface are passivated by hydrogen atoms, hence the initial characteristics are similar. Since the large grain of poly-Si initially generates more dangling bonds in the grain boundaries, after NBTI, hydrogen depassivation generates more grain boundary traps and causes much more serious degradation in device performance.
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    Abnormal C-V Hump Effect Induced by Hot Carriers in Gate Length-Dependent p-Type LTPS TFTs
    (2019-11-01)
    Huang, Shin-Ping
    ;
    Chen, Po-Hsun
    ;
    Tsao, Yu-Ching
    ;
    Chen, Hong-Chih
    ;
    Zheng, Yu-Zhe
    We investigate the abnormal current-voltage (C-V) hump effect of p-type low-temperature polysilicon (LTPS) thin-film transistors (TFTs) which have undergone high current operations. Experimental results indicate localized electron trapping in the gate insulator (GI), which is carried out near the drain. The ON-current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) enhancement is due to the reduction of effective length, and the OFF-current ( ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ ) decrease as the electron tunneling path distance increases. These can be observed after hot carrier stress in current characteristics. The C-V measurements demonstrate that the threshold voltage ( ${V}_{\text {th}}$ ) shift is associated with the gate length. In addition, capacitance-voltage measurements also show that this localized trapping region remains the same in length, regardless of channel length. Hence, a model is proposed to explain how the electric field, which is gate length-dependent, affects the source side of the device, and then lowers the source barrier height. This leads to bulk leakage, which causes the subthreshold swing degradation at device scale down.