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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Huang, TY

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Now showing 1 - 10 of 149
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    Resist-related damage on ultrathin gate oxide during plasma ashing
    (1997-02-01)
    Chien, CH
    ;
    Chang, CY
    ;
    Lin, HC
    ;
    Chang, TF
    ;
    Chiou, SG
    This paper presents an important observation of plasma-induced damage on ultrathin oxides during O-2 plasma ashing by metal ''antenna'' structures with photoresist on top of the electrodes, It is found that for MOS capacitors without overlying photoresist during plasma ashing, only minor damage occurs on thin oxides, even for oxide thickness down to 4.2 nm and an area ratio as large as 10(4), In contrast, oxides thinner than 6 nm with resist overlayer suffer significant degradation from plasma charging, This phenomenon is contrary to most previous reports, It suggests that the presence of photoresist will substantially affect the plasma charging during ashing process, especially for devices with ultrathin gate oxides.
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    Improvements on electrical characteristics of p-channel metal-oxide-semiconductor field effect transistors with HfO2 gate stacks by post deposition N2O plasma treatment
    (2005-11-01)
    Lu, WT
    ;
    Chien, CH
    ;
    Lan, WT
    ;
    Lee, TC
    ;
    Yang, MJ
    In this work, we found that employing a post deposition N2O plasma treatment following the deposition of HfO2 film can effectively improve the electrical characteristics of p-type channel metal-oxide-semiconductor field-effect transistors (pMOSFETs) with a HfO2 gate stack in terms of lower gate leakage current, lower interface state density, superior subthreshold swing, higher normalized transconductance and enhanced driving current even though it had led to a slightly higher equivalent oxide thickness (EOT) value of the HfO2 gate stack by around 0.3 nm. In order to clarify the attributes of the improvements, we used charge pumping (CP) measurement to analyze the densities of interface states and bulk traps in the HfO2 gate stacks. The improvements are then ascribed to the higher interface quality offered by the post deposition N2O plasma treatment. Moreover, we found that to more accurately estimate the bulk traps from the CP measurement, the leakage should be taken into account especially at low frequencies. Finally, it was found that the levels of the bulk traps and interface states can be reduced by the N2O plasma treatment, which also helps significantly eliminate the degradation of the gate stack during the subsequent voltage stress.
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    The role of resist for ultrathin gate oxide degradation during O-2 plasma ashing
    (1997-05-01)
    Chien, CH
    ;
    Chang, CY
    ;
    Lin, HC
    ;
    Chiou, SG
    ;
    Huang, TY
    During ashing process, resist has been intuitively regarded as a protection layer and deliberately removed in previous studies by wet process prior to plasma exposure in an effort to amplify the damage effect, Recently, we found instead that resist does not simply act as a protection layer, This newly observed phenomenon cannot be explained by the well-known electron shading effect which should not affect the area-intensive antenna structure used in our study, In this letter, we hypothesize that this resist-related charging damage is determined by the plasma potential adjustment difference between those devices with and without resist overlayer, The experimental results show a good correlation with our explanation, To be specific, severe antenna area ratio (ARR) dependent degradation of thin gate oxide is induced during the initial ashing stage while the resist is still on the electrodes, not during the overashing period.
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    Improvement of reliability of metal-oxide semiconductor field-effect transistors with N2O nitrided gate oxide and N2O polysilicon gate reoxidation
    (1998-10-01)
    Lai, CS
    ;
    Chao, TS
    ;
    Lei, TF
    ;
    Lee, CL
    ;
    Huang, TY
    A systematic study of the impact of the reliability of metal-oxide semiconductor field-effect transistors (MOSFETs) with N2O nitrided gate oxides and N2O poly-reoxidation was conducted. The improvements include hot carrier immunity, suppression of reverse short channel effect and suppression of plasma-induced degradation. These improvements are due to nitrogen incorporation at the oxide/Si-substrate interface. All data presented in this study involve substantially low thermal budget (850 degrees C), making this N2O-related technology extremely attractive and promising for future scaled devices.
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    A study on the radiation hardness of flash cell with horn-shaped floating-gate
    (1997-09-01)
    Huang, TY
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    Jong, FC
    ;
    Chao, TS
    ;
    Lin, HC
    ;
    Leu, LY
    The effects of radiation on the characteristics of split-gate electrical erasable programmable read only memory (EEPROM)/flash cells with recently-proposed horn-shaped floating gates are studied in terms of cell read current; data retention, cycling endurance, program/erase efficiency, threshold voltage and junction leakage. Our results show that the cells appear to survive after 1 Mrad (Si) Co-60 irradiation. Moreover, the after-irradiation cell read current actually increases in the ''erase'' (i.e., low-threshold voltage, high-conducting) state (i.e., improves), albeit the cell read current also increases in the ''program'' (i.e., high-threshold voltage, low-conducting) state (i.e., a degradation). Our results also show that, despite an improvement in the initial read current in the ''erase'' state immediately after radiation, the write/erase cycling endurance of the flash cells is significantly impeded after irradiation, due to a much faster ''window closure'' rate in the ''erase'' state, although the cell read current is found to remain relatively stable in the ''program'' state after cycling.
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    Physical and electrical characterization of ZrO2 gate insulators deposited on Si(100) using Zr(O-i-Pr)(2)(thd)(2) and O-2
    (2002-06-01)
    Chen, HW
    ;
    Huang, TY
    ;
    Landheer, D
    ;
    Wu, X
    ;
    Moisa, S
    The characteristics of ultrathin ZrO2 films deposited using molecular oxygen and the zirconium precursor Zr(O-i-Pr)(2)(thd)(2) [where O-i-Pr is isopropoxide and thd is 2,2,6,6-tetramethyl-3,5-heptanedionate] were investigated. The organometallic was dissolved as a 0.15 M solution in octane and introduced into the deposition chamber using a liquid injection system. The deposition rate was insensitive to molecular oxygen flow but changed with liquid injection rate and was thermally activated in the range 390-550degreesC. No evidence of Zr-C and Zr-Si bonds were found in the X-ray photoelectron spectroscopy (XPS), spectra, and carbon concentrations, 0.1 atom %, the detection limit of the XPS depth profiling measurements, were obtained at the lowest deposition temperatures and deposition rates. High-resolution transmission electron microscopy showed the ZrO2 films to be polycrystalline as deposited, with an amorphous zirconium silicate interfacial layer. The effects of postdeposition annealing were also demonstrated. After proper annealing treatments, promising capacitance-voltage and current-voltage characteristics were achieved. A film with an equivalent oxide thickness of 2.3 nm showed current reductions of approximately two orders of magnitude when compared to SiO2, but some improvements are required if these films are to be used as a gate-insulator beyond the 100 nm CMOS (complementary metal oxide semiconductor) technology node. (C) 2002 The Electrochemical Society.
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    Characterization of antenna effect by nondestructive gate current measurement
    (1996-08-15)
    Lin, HC
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    Chien, CH
    ;
    Huang, TY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A novel method is proposed for the effective characterization of plasma-charge-induced damage on thin gate oxides. We have found that the gate current measured at V-g(gate voltage) = V-th(threshold voltage) under a low drain bias (e.g., 0.1 V) is a good indicator of the damage. Since the proposed method requires only low bias voltages, it does not cause additional damage to the devices. The proposed gate current measurement is also easy to incorporate to device measurement routines without an extra stressing step, and thus provides a simple and efficient damage indicator for studying plasma-charge-induced damage.
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    Effects of N2O-annealed sacrificial oxide on the short-channel effects of nMOSFETs
    (1998-02-19)
    Jong, FC
    ;
    Huang, TY
    ;
    Chao, TS
    ;
    Lin, HC
    ;
    Wang, MF
    The authors report the effects of N2O-annealed sacrificial oxide on nMOSFETs. It is demonstrated that by adding an N2O-annealing step to the sacrificial. oxide which was stripped off before growing the final gate oxide, the reverse short-channel effects (RSCE) can still be effectively suppressed.
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    Evaluation of plasma charging damage in ultrathin gate oxides
    (1998-03-01)
    Lin, HC
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    Chen, CC
    ;
    Chien, CH
    ;
    Hsein, SK
    ;
    Wang, MF
    Monitoring of plasma charging damage in ultrathin oxides (e.g., <4 nm) is essential to understand its impact on device reliability. However, it is observed that the shift of several device parameters, including threshold voltage, transconductance, and subthreshold swing, are not sensitive to plasma charging and thus not suitable for this purpose. Consequently, some destructive methods, such as the charge-to-breakdown measurement, are necessary to evaluate plasma damage in the ultrathin oxides.
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    Rugged surface polycrystalline silicon film formed by rapid thermal chemical vapor deposition for dynamic random access memory stacked capacitor application
    (1998-06-01)
    Lin, M
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    Chang, CY
    ;
    Huang, TY
    ;
    Kuo, UJ
    ;
    電子工程學系及電子研究所
    Polycrystalline silicon films with a rugged surface (rugged poly-Si), deposited by a single-wafer rapid thermal chemical vapor deposition (RTCVD) system suitable for 12 inch wafer fabrication, are studied and the films have been successfully applied to bottom storage electrodes for stacked capacitors in dynamic random access memory cells. Our data show that the rugged poly-Si is actually formed by the nucleation generation on the amorphous silicon surface and subsequent crystalline growth during the annealing step following deposition. We also determined that a wide temperature window exists for the formation of rugged poly-Si (i.e., +/- 15 degrees C) using RTCVD, which is wider than that using low pressure chemical vapor deposition (LPCVD) (i.e., +/-3 degrees C) and ultra high vacuum chemical vapor deposition (UHVCVD) (i.e., +/-10 degrees C). Stacked capacitors fabricated using rugged poly-Si and thin silicon oxide/silicon nitride dielectric film show that for a rugged poly-Si storage electrode with a 60 nm top-layer and 645 degrees C annealing, an effective surface area of approximately 2.9 times that of a conventional poly-Si film electrode is obtained.