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Asymmetric gate capacitance and dynamic characteristic fluctuations in 16 nm bulk MOSFETs due to random distribution of discrete dopants
(2010-04-01)
Lee, Kuo-Fu
;
Li, Yiming
;
Hwang, Chih-Hong
;
電子工程學系及電子研究所
;
電信工程研究所
Characteristic variability of a transistor is a crucial issue for nanoscale metal-oxide-semiconductor field-effect transistors (MOSFETs). In this study, we explore the asymmetric sketch of the random dopant distribution near the source end and the drain end in 16 nm MOSFETs. Discrete dopants near the source and drain ends of the channel region induce rather different fluctuations in gate capacitance and dynamic characteristics. Based upon the observed asymmetry properties, a lateral asymmetry channel doping profile engineering is then proposed to suppress the random-dopant-induced characteristic fluctuations in the examined devices and circuits. The results of this study indicate that the fluctuations in average gate capacitance, circuit gain, 3 db bandwidth and unity-gain bandwidth for the cases with dopants near the drain side could be simultaneously reduced by 62.6%, 22.2%, 63.1% and 41.4%, respectively. Consequently, such a lateral asymmetry channel doping profile could be considered to design intrinsic parameter fluctuation resistant transistors.
Asymmetric Gate Capacitance and High Frequency Characteristic Fluctuations in 16 nm Bulk MOSFETs Due to Random Distribution of Discrete Dopants
(2008)
Li, Yiming
;
Hwang, Chih-Hong
;
Yeh, Ta-Ching
;
電信工程研究所
;
Institute of Communications Engineering
Discrete-dopant-fluctuated threshold voltage roll-off in sub-16 nm bulk fin-type field effect transistors
(2008-04-01)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
The effect of the number and position of discrete dopants on device characteristics is crucial in determining the behavior of nanoscale semiconductor devices. We explore the fluctuations of threshold voltage (V(th)) roll-off in nanoscale bulk fin-type field effect transistors (FinFETs) by a three-dimensional (3D) statistically full-scale "atomistic" device simulation technique. The explored devices are of three different dimensions: 16, 22, and 30 nm(3). Discrete dopants are statistically positioned into the 3D channel region to explore associated carrier transport characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For the device with a gate length of 16 nm, the V(th) fluctuation of FinFETs is only half that of planar metal-oxide-semiconductor (MOS) FET. Compared with planar MOSFETs, the bulk FinFETs can significantly suppress the fluctuation of V(th) roll-off. The standard deviation of V(th) is proportional to (WL)(-0.25), which is better than the (WL)(-0.5) of planar devices. The superior immunity against fluctuation and the stable fluctuation of V(th) roll-off indicate the bulk FinFET to be a promising device for the sub-16 nm technology era.
Large-scale "atomistic" approach to discrete-dopant-induced characteristic fluctuations in silicon nanowire transistors
(2008-06-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Huang, Hsuan-Ming
;
電信工程研究所
;
Institute of Communications Engineering
Nanowire fin-typed field effect transistors (FinFETs) are ultimate structures and potential candidates for next generation nanoelectronic devices. Due to the limitation of manufacturability, nanowire transistors with a perfect gate structure (i.e., a surrounding gate with 100% gate-coverage ratio) theoretically are not always guaranteed. Impact of the discrete dopants on device performance is crucial in determining the behaviour of nanoscale semiconductor devices. The immunity of nanowire transistor against random discrete-dopant-induced fluctuation may suffer from the variation of gate-coverage-ratio. Therefore, in this paper, we for the fist time study the impact of non-ideal gate coverage on immunity against random-dopant-induced fluctuations for nanowire FinFETs. A 3D statistically sound "atomistic" approach for analyzing random-dopant effect in nanodevice is presented. Discrete dopants are statistically positioned into the channel region to examine associated carrier transportation characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". Our results confirm that the influence of non-ideal gate coverage disturbs the,channel controllability of nanowire FinFETs and thus decreases the immunity against discrete-dopant-induced fluctuation. This study provides an insight into them problem of fluctuation in nanowire transistors and,shows the importance of gate-coverage ratio on device's immunity against discrete-dopant-induced fluctuation. (C) 2008 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim.
Discrete-Dopant-Fluctuated Transient Behavior and Variability Suppression in 16-nm-Gate Complementary Metal-Oxide-Semiconductor Field-Effect Transistors
(2009-04-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Cheng, Hui-Wen
;
電信工程研究所
;
Institute of Communications Engineering
Variability in the characteristics of nanoscale complementary metal-oxide-semiconductor (CMOS) field-effect transistors is a major challenge to scaling and integration. However, little attention has been focused on the existence of transient behavior fluctuations of devices owing to random dopant placement. In this study, we explore the discrete-dopant-induced transient behavior fluctuations of 16-nm-gate CMOS circuits through a three-dimensional large-scale statistically sound "atomistic" device-circuit-coupled simulation approach, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For a 16-nm-gate CMOS inverter, a 3.5% variation of the rise time, a 2.4% variation of the fall time, an 18.3% variation of the high-to-low delay time, and a 13.2% variation of the low-to-high delay time are estimated and discussed. Fluctuation suppression techniques proposed from the device and the circuit viewpoints are implemented to examine the associated intrinsic fluctuations. (C) 2009 The Japan Society of Applied Physics
Temperature dependence on the contact size of GeSbTe films for phase change memories
(2008-09-01)
Li, Yiming
;
Yu, Shao-Ming
;
Hwang, Chih-Hong
;
Kuo, Yi-Ting
;
資訊工程學系
In this study, a three-dimensional electro-thermal time-domain simulation is developed for dynamic thermal analysis of Phase change memories (PCMs). The geometry effects of the GeSbTe (GST) materials and the TiN heater are explored through a series of numerical examinations. It is found that the contact size of the GST significantly alters the maximum temperature of the PCMs, compared with the height of the GST films. The heater's aspect ratio also dominates the maximum temperature of the GST material, and the effect of the heater's thickness on the temperature is more evident than its height. One conformal bi-layer GST structure with different electric and thermal conductivities on the GST layers is examined for different applied currents to extract the curve of resistances versus applied currents.
Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
(2009)
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
Lee, Kuo-Fu
;
Cheng, Hui-Wen
This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.
Process-Variation- and Random-Dopant-Induced Static Noise Margin Fluctuation in Nanoscale CMOS and FinFET SRAM Cells
(2009)
Li, Tien-Yeh
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this study, a three-dimensional "atomistic" coupled device-circuit simulation approach is advanced to investigate the process-variation-effect (PVE) and random dopant fluctuation (RDF) induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. Our preliminary results show that the RDF dominates the fluctuation of static noise margin (SNM). As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the normalized RDF-induced SNM fluctuation increases from 4% to 80%. To reduce the device variability induced fluctuation in circuit, a device with vertical-doping-profile and raised V(th) is employed. The SNM is 3 times larger than the original 16-nm-gate SRAM. Moreover, the normalized RDF-induced SNM fluctuation is reduced by a factor of 2.67. Additionally, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor is used to further improve the SNM of SRAM. Due to the superior electrostatic integrity and larger effective device width than planar MOSFETs, the SNM of 16-nm-gate FinFET SRAM is six times larger than the original 16 nm SRAM with five times smaller SNM fluctuation. The study investigates the roll-off characteristics of SNM and provides an insight into design of fluctuation resistant nanoscale SRAM.
Propagation Delay Dependence on Channel Fins and Geometry Aspect Ratio of 16-nm Multi-Gate MOSFET Inverter
(2009)
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Fin-type vertical channel Field Effect Transistors (FETs) are promising alternatives for the sub-32-nm CMOS technologies. This work investigates the impact of fin number and structure on V,h degradation and transient behavior of devices and circuits. Vertical channel transistors with different fin aspect ratio (AR = the fin height / the effective fin width) are explored. The multi-fin FinFETs (AR = 2) has a better channel controllability and a larger device width than tri-gate (AR = 1) and quasi-planar (AR = 0.5) MOSFETs. Though the increase of fin aspect ratio provides larger effective device width and driving current, the gate capacitance is increased also and limits the intrinsic device gate delay. The transient characteristics of single-/multi-fin inverter circuits are then examined by adding the load capacitance of circuits (1 and 10 fF). The added capacitance dominates the overall load capacitance and reduces the impact of the device intrinsic capacitance. The delay time is therefore dominated by the driving current of transistor and the multi-fin circuits performed a smaller delay time than the single-fin circuits. Additionally, the large driving capability of FinFET implies the less impact of load capacitance variation resulted from process variation. The multi-fin FinFETs exhibit better channel controllability against intrinsic parameter variation of active transistor and also mitigate the impact of process variation induced load capacitance variation of interconnect.
Electrical Characteristics of Nanoscale Multi-Fin Field Effect Transistors with Different Fin Aspect Ratio
(2009)
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
Device characteristics of multiple-fin silicon field effect transistors (FETs) arc sensitive to the channel fin aspect ratio (AR = the fin height / the fin width). In this study, dependence of characteristics on AR for single- and multi-fin FETs arc examined by using a three-dimensional device simulation. The threshold voltage (V(th)) variation of triplefin FET is smaller than that of singlc-fin one clue to a relatively larger effective device width. The triple-fin device with FinFET structure (AR = 2) exhibit rather stable V(th) roll-off characteristics owing to more uniform potential distribution inside the channel. The results of our study show that the driving current, transconductance, gate capacitance of FinFETs are superior to that of tri-gate (AR = 1) and quasi-planar (AR = 0.5) FETs. From the, layout viewpoint, FinFETs has the best layout area efficiency; consequently, to design a device with the subthreshold swing < 70 mV/dec, the layout area of FinFETs is L67 and 1.33 times smaller than those of quasi-planar and tri-gate FETs.

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