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Now showing 1 - 10 of 66

Static power analysis for power-driven synthesis
(1998-03-01)
Yuan, SY
;
Chen, KH
;
Jou, JY
;
Kuo, SY
;
電子工程學系及電子研究所
A new static power analysis method for CMOS combinational circuits is presented. This approach integrates the simulation-based method and the plobabilistic method, and can establish the relationships between the primary inputs and the internal nodes in the circuit. Based on the relationships, our approach can also indicate which internal node or input sequence consumes the most power. It is thus suitable for performing power estimation in the synthesis environment for power optimisation. To the best of our knowledge, this is the first attempt to develop a systematic way to symbolically represent the relationships between the primary inputs and the power consumption at every internal node of a circuit. Furthermore, by using the existing piecewise linear delay model, as well as the proposed algorithm, this novel method is also very accurate and efficient. For a set of benchmark circuits, the experimental results show that the power estimated by our technique is within 5% error as compared with that by the exact SPICE simulation, while the execution speed is more than four orders of magnitude speed is faster.
Sensitisable-path-oriented clustered voltage scaling technique for low power
(1998-07-01)
Jou, JY
;
Chou, DS
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Because the average power consumption of CMOS digital circuits is consumption proportional voltage, a clustered voltage scaling (CVS) technique has previously been proposed to reduce power without sacrificing the circuit performance. In this paper the authors propose a path-oriented CVS algorithm, which can take the false paths into account. Extensive experiments are conducted on ISCAS85 benchmark circuits. These experiments show that many more gates can be voltage scaled down in comparison with the original CVS technique. An additional 22% power reduction ratio over that of the original CVS technique is achieved.
Power-oriented partial-scan design approach
(1998-08-01)
Jou, JY
;
Nien, MC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Power consumption and testability are two of major considerations in modern VLSI design. A full-scan method had been used widely in the past, to improve the testability of sequential circuits. Owing to the lower overheads incurred, the partial-scan design has gradually become popular. The authors propose a partial-scan selection strategy which is based on the structural analysis approach and considers the area and power overheads simultaneously. A powerful sample-and-search algorithm is used to find the solution that minimises the user-specified cost function in terms of power and area overheads. The experimental results show that the sample-and-search algorithm derived by the authors can effectively find the best solution of the specified cost function, for almost all circuits, and, on average, the saving of overheads for each specific cost function is significant.
A logical fault model for library coherence checking
(1998-09-01)
Tung, SW
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A library is the basis of modularized design now. Most operations of CAD tools are based on cell definitions in a library. In this paper, we first give a definition of a library and describe the complexity of library verification. A unified automatic test pattern generation and verification environment is then proposed. The amount of library data coherence checking is reduced to functional simulation on different views of the cells. In order to reduce the number of lest vectors and the amount of simulation time, a Port Order Fault (POF) model is proposed. Using the POF model and the sensitized path approach [1] to generate test vectors, the proposed approach could effectively reduce the complexity of the functional test vectors from O(2(n)) to O(n) for cells with n inputs. Using the POF model, the test sequence can also detect timing inconsistency under the verification environment.
Special issue on hardware description languages - Foreword
(1998-09-01)
Jou, JY
;
Lin, YL
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On circuit clustering for area/delay tradeoff under capacity and pin constraints
(1998-12-01)
Huang, JD
;
Jou, JY
;
Shen, WZ
;
Chuang, HH
;
電子工程學系及電子研究所
In this paper, we propose an iterative area/delay tradeoff algorithm to solve the circuit clustering problem under the capacity constraint. It first finds an initial delay-considered area-optimized clustering solution by a delay-oriented depth-first-search procedure. Then, an iterative procedure consisting of several reclustering techniques is applied to gradually trade the area for the performance. We then show that this algorithm can be easily extended to solve the clustering problem subject to both capacity and pin constraints. Experimental results show that our algorithm can provide a complete set of clustering solutions from the area-optimized one to the delay-optimized one for a given circuit. Furthermore, comparing to the existing delay-optimized algorithms, ours achieves almost the same performance but with much less area overhead. Therefore, this algorithm is very useful on solving the timing-driven circuit clustering problem.
A structure-oriented power modeling technique for macrocells
(1999-09-01)
Lin, JY
;
Shen, WZ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To characterize the power consumption of a macrocell, a general method involves recording the power consumption of all possible input transition events in the look-up tables. However, though this approach is accurate, the size of the table becomes very large. In this paper, we propose a new power modeling technique that takes advantage of the structural information of a macrocell, In this approach, a subset of primary inputs and internal nodes in the macrocell are selected as the state variables to build a state transition graph (STG), These state variables can model the steady-state transitions completely. Moreover, by selecting the characterization patterns properly, the STG can also model the glitch power in the macrocell accurately. To further simplify the complexity of the STG, an incomplete power modeling technique is presented. Without losing much accuracy, the property of compatible patterns is exploited for a macrocell to further reduce the number of edges in the corresponding STG, Experimental results show that our modeling techniques can provide SPICE-like accuracy, while the size of the look-up table is significantly reduced.
Internet-based hierarchical floorplan design
(1999-11-01)
Lin, JH
;
Jou, JY
;
Jiang, IHR
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
With the proliferation of the transistor count in VLSI design, more and more design groups try to figure out an efficient way to combine their designs. The Internet features distributed computing and resource sharing. Consequently, a hierarchical design can adequately be solved in the Internet environment. In this paper, we demonstrate the facilitation of the Internet environment by solving the area minimization floorplan problem. We propose the RMG algorithm taking advantage of the Internet. Based on the model of transfer latencies, the RMG algorithm reduces the computing time by shortening the critical path in the floorplan tree. Our experimental results show that the Internet is suitable for Electronic Design Automation (EDA).
On computing the minimum feedback vertex set of a directed graph by contraction operations
(2000-03-01)
Lin, HM
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Finding the minimum feedback vertex set (MFVS) in a graph is an important problem for a variety of computer-aided design (CAD) applications and graph reduction plays an important role in solving this intractable problem. This paper is largely concerned with three new and powerful reduction operations. Each of these operations defines a new class of graphs, strictly larger than the class of contractible graphs [Levy and Low (1988)], in which the MFVS can be found in polynomial-time complexity. Based on these operations, an exact algorithm run on branch and bound manner is developed. This exact algorithm uses a good heuristic to find out an initial solution and a good bounding strategy to prune the solution space. To demonstrate the efficiency of our algorithms, we have implemented our algorithms and applied them to solving the partial scan problem in ISCAS'89 benchmarks. The experimental results show that if our three new contraction operations are applied, 27 out of 31 circuits in ISCAS'89 benchmarks can be fully reduced. Otherwise, only 12 out of 31 can be fully reduced. Furthermore, for all ISCAS'89 benchmarks our exact algorithm can fmd the exact cutsets in less than 3 s (CPU time) on SUN-UltraII workstation. Therefore, the new contraction operations and our algorithms are demonstrated to be very effective in the partial scan application.
An automatic controller extractor for HDL descriptions at the RTL
(2000-07-01)
Liu, CNJ
;
Jou, JY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Extracting controlling finite-state machines can significantly reduce state space and thereby speed functional verification. The controller extraction algorithm uses an approach that frees it from restrictions on HDL code writing style.

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