🏛️國立陽明交通大學機構典藏

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A MMSE Joint Feedback Feed-forward Equalizer for FBMC-OQAM Baseband Receiver in the 60 GHz Band
(2017-12-01)
Liu, Chun-Yi
;
Leong, Edmund Wen Jen
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Wu, Chang-Ting
;
Sie, Meng-Siou
;
Lopez, Henry
In this paper, a minimum mean square error (MMSE) joint feedback feed-forward equalizer (MJFFE) is proposed to deterministically suppress the inter-symbol interference and inter-carrier interference that arose from the filter bank multi-carrier in a long multipath channel of the 60-GHz indoor wireless transmission. The decision device is discarded in the decision feedback loop to reduce error propagation while at the same time applying the MMSE criterion to prevent over compensation influenced by additive white Gaussian noise. As a result, in an non-line-of-sight (NLOS) channel with 7.65-ns rms delay spread, a 3-tap MJFFE provides 3-dB improvement at the bit error rate (BER) 10(-2) crossing and improve error floor effect at the BER 10(-3) crossing, as compared with the 1-tap zero-forcing equalizer. Furthermore, the proposed equalizer coefficients calculation based on linear convolution for the MJFFE is also presented. The hardware complexity achieves 50% reduction by using several methods including multiplexing, memory sharing, and computation element sharing.
All-Digital Synchronization for SC/OFDM Mode of IEEE 802.15.3c and IEEE 802.11ad
(2015-02-01)
Liu, Wei-Chang
;
Wei, Ting-Chen
;
Huang, Ya-Shiue
;
Chan, Ching-Da
;
Jou, Shyh-Jye
In this paper, a detection and estimation scheme and its architecture design for synchronization in 60 GHz indoor wireless transmission are presented. With the complementary Golay sequence based preamble structure, the proposed synchronization scheme is designed to detect the preamble and symbol boundary, estimate the frequency offset within a unified architecture. For the very high sampling speed at 60 GHz transmission, the architecture is designed as 8x-parallelism with feed-forward data path. This architecture supports the single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) transmissions of both IEEE 802.15.3c and IEEE 802.11ad standards. The synchronization module is implemented as a part of a digital baseband receiver for IEEE 802.15.3c. The tolerance of maximum frequency offset is about 114.58 ppm and 171.87 ppm for SC and OFDM mode, respectively. The implementation result shows that it takes about 0.84 mm(2) of area (equivalent to 307 k gate counts). The power consumption is about 59 mW in SC mode and 96 mW in OFDM (HSI) mode when operating at 1.76 GHz and 2.64 GHz chip rate, respectively.
A Digital Golay-MPIC Time Domain Equalizer for SC/OFDM Dual-Modes at 60 GHz Band
(2013-10-01)
Liu, Wei-Chang
;
Yeh, Fu-Chun
;
Wei, Ting-Chen
;
Chan, Ching-Da
;
Jou, Shyh-Jye
In this paper, a digital time domain equalizer (TDE) for 60 GHz radio frequency transmission systems is presented. Significantly, the TDE supports both single carrier (SC) and orthogonal frequency-division multiplexing (OFDM) operation modes for digital baseband receiver. In order to improve the performance, the proposed TDE adopts Golay sequence aided one-shot channel estimation and modified multi-path interference cancellation (MPIC) equalization. Targeting on the line-of-sight (LOS) channel characteristic, MPIC is simplified with single-tap for complexity reduction. From the area efficiency point of view, both SC and OFDM modes are designed within a single hardware to yield 99% of area sharing. The Golay-MPIC TDE structure is realized as feed-forward data path with 8X-parallelism to achieve 2.64 GS/s at 330 MHz clock rate. The Golay-MPIC TDE is fabricated as a part of a digital baseband with 65 nm 1P9M general purpose process. The area of Golay-MPIC TDE occupies 1.05 with 405 K gate counts. Besides, the power dissipations for SC and ODFM modes are 56.71 mW@220 MHz (1 V) and 91.29 mW@330 MHz (1.1 V), respectively. Finally, the chip can provide the maximum throughput 15.84 Gb/s (2.64 GS/s with 64-QAM modulation).
A jointed mode detection and symbol detection scheme for DVB-T
(2008-05-01)
Wei, Ting-Chen
;
Liu, Wei-Chang
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work proposes a jointed mode detection and symbol detection scheme for DVB-T To reduce hardware complexity, the division operation of normalized maximum correlation (NMC) is removed and the delay line which uses twisted memory access method lowers the hardware cost. In addition, the proposed detection procedure does not need to refill or replenish the received data samples; as the result, the longest latency of the detection is only 17280 samples and is comparable with the parallel method. To lower the hardware cost, the memory is released for channel estimation after completing the Mode/GI detection and symbol detection. Total complexity of Mode/GI/symbol detection and channel estimation is about 200 Kgates (including memory)(1).
Low Complexity Synchronization Design of an OFDM Receiver for DVB-T/H
(2009-05-01)
Wei, Ting-Chen
;
Liu, Wei-Chang
;
Tseng, Chi-Yao
;
Jou, Shyh-Jye
;
電子工程學系及電子研究所
In this paper, an OFDM baseband receiver for DVB-T/H is presented. The receiver contains four synchronizations, an OFDM symbol synchronization, a carrier synchronization, a sampling clock synchronization and a scattered pilots synchronization. This paper proposes several novel designs to reduce the synchronization latency and hardware complexity. The carrier and clock synchronization loops are fully digitalized schemes. The scattered pilots synchronization adopts a two stages scheme to reduce the detection latency. In addition, the pre-filling scheme reduces the latency of channel estimation. The design result shows that the equivalent gate count is about 810K gates including 102.8KB memory(1).

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