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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Juang, Ying-ZongHas files: Yes

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    Develop a novel thermal switch through CMOS MEMS fabrication process
    (2011-01-01)
    Lai, You-Liang
    ;
    Chou, Lei-Chun
    ;
    Juang, Ying-Zong
    ;
    Tsai, Hann-Huei
    ;
    Huang, Sheng-Chieh
    This paper focuses on implementing two novel CMOS-MEMS type switches: buckling type and thermal type, by using commercially available TSMC 0.35 mu m two-poly four-metal (2P4M) CMOS process. There are two novel designs in these two type switches: first, the soft contact structure with post-processing fabrication; second, using residual stress to achieve large structural deformation in buckling type and thermal type switches. To create the soft contact structure, residual gradient stress effect has been utilized to make bending-down curvatures. According to the experiments, the layer Metal1 has the largest negative residual gradient stress [1] effect that can achieve the largest negative deflection in z-axis. Because the structure will bend down after post-processing release, larger lateral contact area are set up to gain the lower contact miss ability. In the post-processing fabrication, 0.3 mu m thickness gold will be deposited on the contact tips. Due to the essence of gold, comparing with aluminum, has no oxidation issue, gold also has the advantage of higher conductivity to reduce the electrical power loss. In the buckling type design, the switch uses residual stress to achieve lateral buckling effect to solve long distance problem. In the thermal type design, this paper design a folded-flexure [2, 3] with the electro-thermal excitation to turn the switch on or off. In the prototype, the device size is 500 mu m x 400 mu m and the gap between two contact pads is 9 mu m in off-state. on the experimental results, the switch can work stably at 3 volts, and the displacement of the thermal type switch can achieve 2.7 mu m, which is sufficient for the mechanism of switching-on or switching-off.
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    Thermal switch design by using complementary metal-oxide semiconductor MEMS fabrication process
    (2011-07-01)
    Chiou, Jin-Chern
    ;
    Chou, Lei-Chun
    ;
    Lai, You-Liang
    ;
    Juang, Ying-Zong
    ;
    Huang, Sheng-Chieh
    The present study focuses on implementing a complementary metal-oxide semiconductor (CMOS) microelectromechanical system thermal switch by using the commercially available Taiwan Semiconductor Manufacturing Company (TSMC) 0.35 mu m two-poly four-metal CMOS process. There are two novel designs: first, the soft contact structure and post-processing fabrication; second, a new design of thermal actuator. To create the soft contact structure, residual stress effect has been utilised to make different bending curvatures. According to the experiments, the layer metal-1 has the largest residual stress effect that can achieve the largest deflection in the z-axis. Because the residual stress of the layer metal-1 is negative, the structure will bend down after release, hence providing larger contact area, which has been set up to obtain the lowest contact miss ability. In the post-processing fabrication, 0.3 mu m thickness gold will be patterned at the contact tips. Since gold, rather than aluminium, has no oxidation issue, it has more reliability in preventing the problem of oxidation than aluminium. In the new thermal actuator design, the authors designed a novel folded-flexure with the electrothermal excitation to turn the switch on or off. In the prototype, the device size is 500 x 400 mu m and the gap between two contact pads is 9 mu m in off-state. Depending on the simulation results, the switch can work stably at 3 V, and the working temperature and operating bandwidth are individually 20-200 degrees C.
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    Experimental Verification of RF Stress Effect on Cascode Class-E PA Performance and Reliability
    (2012-06-01)
    Yuan, Jiann-Shiun
    ;
    Yen, Hsuan-Der
    ;
    Chen, Shuyu
    ;
    Wang, Ruey-Lue
    ;
    Huang, Guo-Wei
    A cascode class-E power amplifier (PA) operating at 5.2 GHz has been designed using Advanced Design System simulation. RF circuit performances such as output power and power-added efficiency before and after RF stress have been experimentally investigated. The measured output power, power-added efficiency, and linearity after high-input-power RF stress at elevated supply voltage show significant circuit degradations. The impact of hot-carrier injection and gate oxide soft breakdown on cascode class-E PA reliability is discussed.
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    Design and fabrication of a CMOS MEMS logic gate
    (2011)
    Tsai, Chun-Yin
    ;
    Chen, Tsung-Lin
    ;
    Liao, Hsin-Hao
    ;
    Lin, Chen-Fu
    ;
    Juang, Ying-Zong
    This study aims to develop a novel CMOS-MEMS logic gate via commercially available CMOS process (TSMC, 2P4M (R)). Compared to existing CMOS MEMS designs, which uses foundry processes, the proposed design imposes several new challenges including: carrying two voltage levels on a non-warping suspended plate, metal-to-metal contact, and etc. Different combinations of oxide-metal films and post-CMOS process are investigated to achieve a non-warping suspended structure layer. And different wet etchants are investigated to remove sacrificial layers without attacking structure layers and features. In a prototype design, the selected structure layer is metal-3 and oxide film; the device is released using AD-10 and titanium etchant; the device is 250 mu m long, 100 mu m wide, and 1.5 mu m gap. The experimental results show that the suspended plate slightly curls down 0.485 mu m. This device can be actuated by 10/0 V with a moving distance 50nm. The resonant frequency is measured at 36 kHz. Due to the damage of the tungsten plugs, the logic function can only be verified by its mechanical movements instead of electrical readouts for now.
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    A 2.4-5.4-GHz Wide Tuning-Range CMOS Reconfigurable Low-Noise Amplifier
    (2008-12-01)
    Fu, Chang-Tsung
    ;
    Ko, Chun-Lin
    ;
    Kuo, Chien-Nan
    ;
    Juang, Ying-Zong
    ;
    電子工程學系及電子研究所
    A 2.4-5.4-GHz CMOS reconfigurable low-noise amplifier (LNA) is designed. It consists of two stages: a broadband input stage for a steady input matching and noise performance, and a reconfigurable band-selective stage which provides a wide-range frequency tuning from 2.4 to 5.4 GHz and a 12-dB stepped gain with linearity adjustment. The frequency tuning is conducted by a multitapped switching inductor and varactors. Careful design of the switching inductor achieves consistent performance among frequency configurations. The stepped gain and linearity adjustment are provided by a size-switchable transistor with a variable biasing. Fabricated in 0.13 mu m CMOS technology this LNA exhibits performance including up to 25 dB power gain, 2.2-3.1 dB noise figure and less than 5 mW power consumption under 1 V power supply.