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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Kao, Kuo-HsingHas files: Yes

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Now showing 1 - 8 of 8
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    Improvement on performance and reliability of TaN/HfO2 LTPS-TFTs with fluorine implantation
    (2008-03-01)
    Ma, Ming-Wen
    ;
    Chen, Chih-Yang
    ;
    Su, Chun-Jung
    ;
    Wu, Woei-Cherng
    ;
    Yang, Tsung-Yu
    In this paper, we demonstrate the low-temperature polycrystalline silicon thin-film transistors (LTPS-TFTs) with TaN metal-gate and HfO2 gate dielectric to achieve high performance characteristics. A high performance LTPS-TFT with low threshold voltage 0.9 V, excellent subthreshold swing 0.15 V/decade and high I-on/I-min current ratio 1.9 x 10(6) are derived without any hydrogen treatment. In addition, we also introduce the fluorine implantation prior to the Si thin-film crystallization to passivate the defects in grain-boundaries of the channel film and HfO2/polysilicon interface. Significant improvements on subthreshold swing and I-min are observed. In addition, the transconductance degradation and threshold voltage instability due to hot carrier stress is also investigated, respectively. Finally, we derive a high reliability and performance LTPS-TFT with low threshold voltage similar to 1.38 V, ultra-low subthreshold swing 0.132 V/decade and high I-on/I-min current ratio 1.21 x 10(7), which is suitable for the application of system-on panel (SOP). (c) 2007 Elsevier Ltd. All rights reserved.
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    Fringing electric field effect on 65-nm-node fully depleted silicon-on-insulator devices
    (2006-09-01)
    Ma, Ming-Wen
    ;
    Chao, Tien-Sheng
    ;
    Kao, Kuo-Hsing
    ;
    Huang, Jyun-Siang
    ;
    Lei, Tan-Fu
    In this study, the fringing electric field effect on 65-nm-node technology fully depleted silicon-on-insulator (FD SOI) device is comprehensively examined. A new anomalous degradation in device on-state/off-state characteristics on a nanoscale metaloxide-semiconductor field-effect transistor (MOSFET) with high-kappa gate dielectrics is reported, the so-called fringing-induced barrier lowering (FIBL). This is due to the decrease in fringing electric field and increase in the gate dielectric thickness when gate dielectric permittivity increased. We observe that FIBL can be effectively suppressed using a stack gate dielectric structure. In addition, we also implement a high-kappa offset spacer to further improve the on-state driving current I-on to approximately 26% higher than that of a conventional silicon dioxide offset spacer and reduce the off-state leakage current I-off by about 34%. This benefit is due to the enhanced high vertical channel electric field obtained via the offset spacer using a high-kappa material as a spacer. This enhanced fringing electric field can markedly increase I-on/I-off current ratio and reduce subthreshold swing (S-factor) to improve MOSFET performance, which implies that gate-to-channel controllability can be improved markedly. This would play an important role beyond the 65-nm-node technology.
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    High-kappa material sidewall with source/drain-to-gate non-overlapped structure for low standby power applications
    (2006-11-01)
    Ma, Ming-Wen
    ;
    Chao, Tien-Sheng
    ;
    Kao, Kuo-Hsing
    ;
    Huang, Jyun-Siang
    ;
    Lei, Tan-Fu
    In this paper, fully depleted silicon-on-insulator (SOI) devices with source/drain extension shifts and a high-kappa offset spacers were investigated in detail. The calculated results show that the source/drain extension shift can decrease off-state leakage current I-off significantly by utilizing the extra electron barrier height in the source/drain extension shift region to reduce standby power dissipation. However, the on-state driving current In is also sacrificed simultaneously. To overcome this drawback, a high-kappa offset spacer is used to increase the on-state driving current I-on effectively by enhancing the vertical fringing electric field which elevates the channel voltage drop and reduces series resistance.
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    Impact of high-k offset spacer in 65-nm node SOI devices
    (2007-03-01)
    Ma, Ming-Wen
    ;
    Wu, Chien-Hung
    ;
    Yang, Tsung-Yu
    ;
    Kao, Kuo-Hsing
    ;
    Wu, Woei-Cherng
    In this letter, 65-nm node silicon-on-insulator devices with high-k, offset spacer dielectric were investigated by extensive 2-D device simulation. The result shows that the high-k, offset spacer dielectric can effectively increase the ON-state driving current I-ON and reduce the OFF leakage current I-OFF due to the high vertical fringing electric field effect. This fringing field can significantly improve the I-ON/I-OFF current ratio and the subthreshold swing compared with the conventional oxide spacer. Consequently, the gate-to-channel control ability is enhanced by the fringing field via the high-k offset spacer dielectric.
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    Characteristics of PBTI and hot carrier stress for LTPS-TFT with high-kappa gate dielectric
    (2008-02-01)
    Ma, Ming-Wen
    ;
    Chen, Chih-Yang
    ;
    Su, Chun-Jung
    ;
    Wu, Woei-Cherng
    ;
    Wu, Yi-Hong
    In this letter, the characteristics of positive bias temperature instability (PBTI) and hot carrier stress (HCS) for the low-temperature poly-Si thin-film transistors (LTPS-TFTs) with HfO2 gate dielectric are well investigated for the first time. Under room temperature stress condition, the PBTI shows a more serious degradation than does HCS, indicating that the gate bias stress would dominate the hot carrier degradation behavior for HfO2 LTPS-TFT. In addition, an abnormal behavior of the I-min degradation with different drain bias stress under high-temperature stress condition is also observed and identified in this letter. The degradation of device's performance under high-temperature stress condition can be attributed to the damages of both the HfO2 gate dielectric and the poly-Si grain boundaries.
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    Impacts of fluorine ion implantation with low-temperature solid-phase crystallized activation on high-kappa LTPS-TFT
    (2008-02-01)
    Ma, Ming-Wen
    ;
    Chen, Chih-Yang
    ;
    Su, Chun-Jung
    ;
    Wu, Woei-Cherng
    ;
    Wu, Yi-Hong
    In this letter, fluorine ion implantation with low-temperature solid-phase crystallized activation scheme is used to obtain a high-performance HfO2 low-temperature poly-Si thin-film transistor (LTPS-TFT) for the first time. The secondary ion mass spectrometer (SIMS) analysis shows a different fluorine profile compared to that annealed at high temperature. About one order current reduction of I-min is achieved because 25% grain-boundary traps are passivated by fluorine implantation. In addition, the threshold voltage instability of hot carrier stress is also improved with the introduction of fluorine. The LTPS-TFT with HfO2 gate dielectric and fluorine preimplantation can simultaneously achieve low V-TH similar to 1.32 V, excellent subthreshold swing similar to 0.141 V/dec, and high I-ON/I-min current ratio 1.98 x 10(7).
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    Reliability mechanisms of LTPS-TFT with HfO2 gate dielectric: PBTI, NBTI, and hot-carrier stress
    (2008-05-01)
    Ma, Ming-Wen
    ;
    Chen, Chih-Yang
    ;
    Wu, Woei-Cherrig
    ;
    Su, Chun-Jung
    ;
    Kao, Kuo-Hsing
    In this paper, a comprehensive study of the reliability mechanisms of high-performance low-temperature polycrystalline-Si thin-film transistor (LTPS-TFT) with HfO2 gate dielectric is reported for the first time. Various bias- and temperature-stress conditions, which correspond to positive-bias stress (PBS), positive-bias temperature instability (PBTI), negative-bias stress (NBS), negative-bias temperature instability (NBTI), and hot-carrier stress, are used to differentiate the distribution and mechanism of trap density states. The generation of deep-trap states of the effective interfacial layer (IL), tail-trap states of poly-Si grain boundaries, and electron trapping of the HfO2 gate dielectric is observed for the PBS and PBTI of the HfO2 LTPS-TFT. In addition, both the deep- and tail-trap states of the effective IL are generated under NBS and NBTI of the HfO2 LTPS-TFT.
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    High-performance metal-induced laterally crystallized polycrystalline silicon p-channel thin-film transistor with TaN/HfO2 gate stack structure
    (2008-06-01)
    Ma, Ming-Wen
    ;
    Chao, Tien-Sheng
    ;
    Su, Chun-Jung
    ;
    Wu, Woei-Cherng
    ;
    Kao, Kuo-Hsing
    In this letter, high-performance low-temperature poly-Si p-channel thin-film transistor with metal-induced lateral-crystallization (MILC) channel layer and TaN/HfO2 gate stack is demonstrated for the first time. The devices of low threshold voltage V-TH similar to 0.095 V, excellent subthreshold swing S.S. similar to 83 mV/dec., and high field-effect mobility mu(FE) similar to 240 cm(2)/V center dot s are achieved without any defect passivation methods. These significant improvements are due to the MILC channel film and the very high gate-capacitance density provided by HfO2 gate dielectric with the effective oxide thickness of 5.12 mn.