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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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Now showing 1 - 8 of 8

Improved output ESD protection by dynamic gate floating design
(1998-09-01)
Chang, HH
;
Ker, MD
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A dynamic gate Boating design is proposed to improve ESD robustness of the CMOS output buffers with small drive capability. By using this novel design, the human-body-model (machine-model) ESD failure threshold of a 2-mA CMOS output buffer has been practically improved from 1 KV (100 V) to greater than 8 KV (1500 V) in a 0.35-mu m CMOS process.
Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
(2000-04-01)
Ker, MD
;
Lo, WY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new design on the diode string with very tow leakage current is proposed for using in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the Leakage current of this new diode string with six stacked diodes at 5-V (3.3-V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125 degrees C in a 0.35-mu m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA, The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35-mu m silicide CMOS process by using neither the ESD-implantation nor the silicide-blocking process modifications.
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
(2002-06-01)
Ker, MD
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using the thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35-mum CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 mum can be obviously improved from the original similar to2 kV to be greater than 8 kV by this SNTSCR device with a device dimension of only 60 mum/0.35 mum.
Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
(2002-11-15)
Ker, MD
;
Hsu, HC
;
Peng, JJ
;
電機學院
;
College of Electrical and Computer Engineering
A novel ion implantation method for electrostatic discharge protection, often called as ESD implantation, is proposed to significantly improve machine-model (MM) ESD robustness of N-channel metal-oxide semiconductors (NMOS) device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L = 300 mum/0.5 mum for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-mum complementary metal-oxide semiconductors (CMOS) process.
ESD implantation for subquarter-micron CMOS technology to enhance ESD robustness
(2003-10-01)
Ker, MD
;
Hsu, HC
;
Peng, JJ
;
電機學院
;
College of Electrical and Computer Engineering
A new electrostatic discharge (ESD) implantation method is proposed to significantly improve ESD robustness of CMOS integrated circuits in subquarter-micron CMOS processes, especially the machine-model (MM) ESD robustness. By using this method, the ESD current is discharged far away from the surface channel of nMOS, therefore the nMOS (both single nMOS and stacked nMOS) can sustain a much higher ESD level. The MM ESD robustness of the gate-grounded nMOS with a device dimension width/length (W/L) of 300 mum/0.5 mum has been successfully improved from the original 450 V to become 675 V in a 0.25-mum CMOS process. The MM ESD robustness of the stacked nMOS in the mixed-voltage I/O circuits with a device dimension W/L of 300 mum/0.5 mum for each nMOS has been successfully improved from the original 350 V to become 500 V in the same CMOS process. Moreover, this new ESD implantation Method with the n-type impurity can be fully Merged into the general subquarter-micron CMOS processes.
Dummy-gate structure to improve turn-on speed of silicon-controlled rectifier (SCR) device for effective electrostatic discharge (ESD) protection
(2003-11-15)
Ker, MD
;
Hsu, KC
;
電機學院
;
College of Electrical and Computer Engineering
Turn-on speed is the main concern for on-chip electrostatic discharge (ESD) protection device, especially, in deep submicron complementary metal-oxide semiconductors (CMOS) processes with ultra-thin gate oxide. A novel dummy-gate-blocking silicon-controlled rectifier (SCR) device with substrate-triggered technique is proposed to improve the turn-on speed of SCR device for using in on-chip ESD protection circuit to effectively protect the much thinner gate oxide. From the experimental results, the switching voltage, turn-on resistance, and turn-on time of substrate-triggered SCR (STSCR) device with dummy-gate structure have been efficiently improved, as compared with the normal SCR with shallow trench isolation (STI) structure.
MOS-bounded diodes for on-chip ESD protection in deep submicron CMOS process
(2005-03-01)
Ker, MD
;
Lin, KH
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
New diode structures without the field-oxide boundary across the p/n junction for ESD protection are proposed. A NMOS (PMOS) is especially inserted into the diode structure to form the NMOS-bounded (PMOS-bounded) diode, which is used to block the field oxide isolation across the p/n junction in the diode structure. The proposed N(P)MOS-bounded diodes can provide more efficient ESD protection to the internal circuits, as compared to the other diode structures. The N(P)MOS-bounded diodes can be used in the I/O ESD protection circuits, power-rail ESD clamp circuits, and the ESD conduction cells between the separated power lines. From the experimental results, the human-body-model ESD level of ESD protection circuit with the proposed N(P)MOS-bounded diodes is greater than 8 kV in a 0.35-mu m CMOS process.
ESD implantations for on-chip ESD protection with layout consideration in 0.18-mu m salicided CMOS technology
(2005-05-01)
Ker, MD
;
Chuang, CH
;
Lo, WY
;
電機學院
;
College of Electrical and Computer Engineering
One method to enhance electrostatic discharge (ESD) robustness of the on-chip ESD protection devices is through process design by adding an extra "ESD implantation" mask. In this work, ESD robustness of nMOS devices and diodes with different ESD implantation solutions in a 0.18 mu m salicided CMOS process is investigated by experimental testchips. The second breakdown current (I-t2) of the nMOS devices with these different ESD implantation solutions for on-chip ESD protection are measured by a transmission line pulse generator (TLPG). The human-body-model (HBM) and machine-model (MM) ESD levels of these devices are also investigated and compared. A significant improvement in ESD robustness is observed when an nMOS device is fabricated with both boron and arsenic ESD implantations. The ESD robustness of the N-type diode under the reverse-biased stress condition can also be improved by the boron ESD implantation. The layout consideration in multifinger MOSFETs and diodes for better ESD robustness is also investigated.

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