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Design on the low-leakage diode string for using in the power-rail ESD clamp circuits in a 0.35-mu m silicide CMOS process
(2000-04-01)
Ker, MD
;
Lo, WY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new design on the diode string with very tow leakage current is proposed for using in the ESD clamp circuits across the power rails. By adding an NMOS-controlled lateral SCR (NCLSCR) device into the stacked diode string, the Leakage current of this new diode string with six stacked diodes at 5-V (3.3-V) forward bias can be reduced to only 2.1 (1.07) nA at a temperature of 125 degrees C in a 0.35-mu m silicide CMOS process, whereas the previous designs have a leakage current in the order of mA, The total blocking voltage of this new design with NCLSCR can be linearly adjusted by changing the number of the stacked diodes in the diode string without causing latch-up danger across the power rails. From the experimental results, the human-body-model ESD level of the ESD clamp circuit with the proposed low-leakage diode string is greater than 8 kV in a 0.35-mu m silicide CMOS process by using neither the ESD-implantation nor the silicide-blocking process modifications.
On-chip ESD protection design by using polysilicon diodes in CMOS process
(2001-04-01)
Ker, MD
;
Chen, TY
;
Wang, TH
;
Wu, CY
;
電子工程學系及電子研究所
A novel on-chip electrostatic discharge (ESD) protection design by using polysilicon diodes as the ESD clamp devices in CMOS process is first proposed in this paper, Different process splits have been experimentally evaluated to find the suitable doping concentration for optimizing the polysilicon diodes for both on-chip ESD protection design and the application requirements of the smart-card ICs. The secondary breakdown current (It2) of the polysilicon diodes under the forward- and reverse-bias conditions has been measured by the transmission-line-pulse (TLP) generator to investigate its ESD robustness, Moreover, by adding an efficient VDD-to-VSS clamp circuit into the IC, the human-body-model (HBM) ESD robustness of the IC with polysilicon diodes as the ESD clamp devices has been successfully improved from the original similar to 300 V to become greater than or equal to3 kV, This design has been practically applied in a mass-production smart-card IC.
Stacked-NMOS triggered silicon-controlled rectifier for ESD protection in high/low-voltage-tolerant I/O interface
(2002-06-01)
Ker, MD
;
Chuang, CH
;
電機學院
;
College of Electrical and Computer Engineering
A stacked-NMOS triggered silicon-controlled rectifier (SNTSCR) is proposed as the electrostatic discharge (ESD) clamp device to protect the mixed-voltage I/O buffers of CMOS ICs. This SNTSCR device is fully compatible to general CMOS processes without using the thick gate oxide to overcome the gate-oxide reliability issue. ESD robustness of the proposed SNTSCR device with different layout parameters has been investigated in a 0.35-mum CMOS process. The HBM ESD level of the mixed-voltage I/O buffer with the stacked-NMOS channel width of 120 mum can be obviously improved from the original similar to2 kV to be greater than 8 kV by this SNTSCR device with a device dimension of only 60 mum/0.35 mum.
Electrostatic discharge protection design for mixed-voltage CMOS I/O buffers
(2002-08-01)
Ker, MD
;
Chuang, CH
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new electrostatic discharge (ESD) protection circuit, using the stacked-nMOS triggered silicon controlled rectifier (SNTSCR) as the ESD clamp device, is designed to protect the mixed-voltage I/O buffers of CMOS ICs. The new proposed ESD protection circuit, which combines the stacked-nMOS structure with the gate-coupling circuit technique into the SCR device, is fully compatible to general CMOS processes without causing the gate-oxide reliability problem. Without using the thick gate oxide, the experimental results in a 0.35-mum CMOS process have proven that the human-body-model ESD level of the mixed-voltage I/O buffer can be successfully increased from the original similar to2 kV to >8 kV by using this proposed ESD protection circuit.
Design and analysis of on-chip ESD protection circuit with very low input capacitance for high-precision analog applications
(2002-09-01)
Ker, MD
;
Chen, TY
;
Wu, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
An ESD protection design is proposed to solve the ESD protection challenge to the analog pins for high-frequency or current-mode applications. By including an efficient power-rails clamp circuit into the analog I/O pin, the device dimension (W/L) of ESD clamp device connected to the I/O pad in the analog ESD protection circuit can be reduced to only 50/0.5 (mum/mum) in a 0.35-mum silicided CMOS process, but it can sustain the human-body-model (machine-model) ESD level of up to 6 kV (400 V). With such a smaller device dimension, the input capacitance of this analog ESD protection circuit can be significantly reduced to only similar to1.0 pF (including the bond pad capacitance) for high-frequency applications. A design model to find the optimized layout dimensions and spacings on the input ESD clamp devices has been also developed to keep the total input capacitance almost constant (within 1% variation), even if the analog input signal has a dynamic range of 1 V.
Novel implantation method to improve machine-model electrostatic discharge robustness of stacked N-channel metal-oxide semiconductors (NMOS) in sub-quarter-micron complementary metal-oxide semiconductors (CMOS) technology
(2002-11-15)
Ker, MD
;
Hsu, HC
;
Peng, JJ
;
電機學院
;
College of Electrical and Computer Engineering
A novel ion implantation method for electrostatic discharge protection, often called as ESD implantation, is proposed to significantly improve machine-model (MM) ESD robustness of N-channel metal-oxide semiconductors (NMOS) device in stacked configuration (stacked NMOS). By using this ESD implantation method, the ESD current is discharged far away from the surface channel of NMOS, therefore the stacked NMOS in the mixed-voltage I/O interface can sustain a much higher ESD level, especially under the MM ESD stress. The MM ESD robustness of the stacked NMOS with a device dimension of W/L = 300 mum/0.5 mum for each NMOS has been successfully improved from the original 358 V to become 491 V in a 0.25-mum complementary metal-oxide semiconductors (CMOS) process.
Substrate-triggered ESD protection circuit without extra process modification
(2003-02-01)
Ker, MD
;
Chen, TY
;
電機學院
;
College of Electrical and Computer Engineering
A substrate-triggered technique is proposed to improve electrostatic discharge (ESD) protection efficiency of ESD protection circuits without extra salicide blocking and ESD-implantation process modifications in a salicided shallow-trench-isolation CMOS process. By using the layout technique, the whole E.SD protection circuit can be merged into a compact device structure to enhance the substrate-triggered efficiency. This substrate-triggered design can increase ESD robustness and reduce the trigger voltage of the ESD protection device. This substrate-triggered ESD protection circuit with a field oxide device of channel width of 150 mum can sustain a human-body-model ESD level of 3250 V without any extra process modification. Comparing to the traditional ESD protection,design of gate-grounded nMOS (ggnMOS) with silicide-blocking process modification in a 0.25-mum salicided CMOS process, the proposed substrate-triggered design without extra process modification can improve ESD robustness per unit silicon area from the original 1.2 V/mum(2) of ggnMOS to 1.73 V/mum(2).
Substrate-triggered SCR device for on-chip ESD protection in fully silicided sub-0.25-mu m CMOS process
(2003-02-01)
Ker, MD
;
Hsu, KC
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The turn-on mechanism of a silicon-controlled rectifier (SCR) device is essentially a current triggering event. While a current is applied to the, base or - substrate of the SCR device, it can be quickly triggered, into its latching state. In this paper, a novel design concept to turn on the SCR device by applying the substrate-triggered technique is first proposed for effective on-chip electrostatic discharge (ESD) protection. This novel substrate-triggered SCR device has the advantages of controllable switching voltage and adjustable holding voltage and is compatible with, general CMOS processes without extra process modification such as the silicide-blocking mask and ESD implantation. Moreover, the substrate-triggered SCR, devices can be stacked in ESD protection circuits to avoid the translient-induced latch-up issue. The turn-on time of the proposed substrate-triggered SCR devices, can be reduced from 27.4 to 7.8 ns by the substrate-triggering, technique. The substrate-triggered SCR device with a small active area of only 20 mum x 20 mum can sustain the HBM ESD stress of 6.5 kV in a fully silicided 0.25-mum CMOS process.
Substrate-triggered technique for on-chip ESD protection design in a 0.18-mu m salicided CMOS process
(2003-04-01)
Ker, MD
;
Chen, TY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The substrate triggered technique for input, output, and power-rail electrostatic discharge (ESD) protection, as,comparing to the traditional gate-driven technique, has been proposed to effectively improve ESD robustness of IC products. With the substrate-triggered technique, on-chip ESD protection circuits tor the input, output, and power pins have been designed and verified in a 0.18-mum salicided CMOS process. The experimental results have confirmed that the proposed substrate-triggered design can effectively and continually improve ESD robustness of CMOS devices. The humari-body-model (HUM) ESD robustness of NMOS with a device dimension of W/L = 300 mum/0.3 mum can be improved from the original 0.65 kV with the traditional gate-driven design to become 3.2 kV with the proposed substrate-triggered design.
High-current characterization of polysilicon diode for electrostatic discharge protection in sub-quarter-micron complementary metal oxide semiconductor technology
(2003-06-01)
Ker, MD
;
Chang, CY
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Polysilicon diodes used in sub-quarter-micron complementary metal oxide semiconductor (CMOS) technologies are characterized by transmission line pulse (TLP) measurement to investigate device characteristics in a high-current regime. The second-breakdown current (I-t2) of the polysilicon diode shows good linear dependence on the device junction perimeter. When the polysilicon diodes are connected in a stacked configuration for reducing parasitic capacitance, the stacked polysilicon diodes show no degradation in electrostatic discharge (ESD) robustness compared with a single polysilicon diode. Such CMOS process-compatible polysilicon diodes have been successfully used as on-chip ESD protection devices for GHz radio-frequency (RF) circuits.

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