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Author: search.filters.author.Ker, MDSubject: search.filters.subject.latchup

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Now showing 1 - 6 of 6
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    Methodology on extracting compact layout rules for latchup prevention in deep-submicron bulk CMOS technology
    (2003-05-01)
    Ker, MD
    ;
    Lo, WY
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    An experimental methodology to find area-efficient compact layout rules to prevent latchup in bulk complimentary metal-oxide-semiconductor (CMOS) integrated circuits (ICs) is proposed. The layout rules are extracted from the test patterns with different layout spacings or distances, A new latchup prevention design by adding the additional internal double guard rings between input/output cells and internal circuits is first reported in the literature, and its effectiveness has been successfully proven in three different bulk CMOS processes. I Through detailed experimental verification including temperature effect, the proposed methodology to extract compact layout rules has been established to save silicon area of CMOS ICs but still to have high enough latchup immunity. This proposed methodology has been successfully verified in a 0.5-mum nonsilicided, a 0.35-mum silicided, and a 0.25-mum silicided shallow-trench-isolation bulk CMOS processes.
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    Double snapback characte'ristics in high-voltage nMOSFETs and the impact to on-chip ESD protection design
    (2004-09-01)
    Ker, MD
    ;
    Lin, KH
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    The double snapback characteristic in the highvoltage nMOSFET under transmission line pulsing stress is found. The physical mechanism of double snapback phenomenon in the high-voltage nMOSFET is investigated by device simulation. With double snapback characteristic in high-voltage nMOSFET, the holding voltage of the high-voltage nMOSFET in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristic will cause the high-voltage CMOS ICs susceptible to the latchup-like danger in the real system applications, especially while the high-voltage nMOSFET is used in the power-rail electrostatic discharge clamp circuit.
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    Overview of on-chip electrostatic discharge protection design with SCR-based devices in CMOS integrated circuits
    (2005-06-01)
    Ker, MD
    ;
    Hsu, KC
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    An overview on the electrostatic discharge (ESD) protection circuits by using the silicon controlled rectifier (SCR)-based devices in CMOS ICs is presented. The history and evolution of SCR device used for on-chip ESD protection is introduced. Moreover, two practical problems (higher switching voltage and transient-induced latchup issue) limiting the use of SCR-based devices in on-chip ESD protection are reported. Some modified device structures and trigger-assist circuit techniques to reduce the switching voltage of SCR-based devices are discussed. The solutions to overcome latchup issue in the SCR-based devices are also discussed to safely apply the SCR-based devices for on-chip ESD protection in CMOS IC products.
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    The impact of low-holding-voltage issue in high-voltage CMOS technology and the design of latchup-free power-rail ESD clamp circuit for LCD driver ICs
    (2005-08-01)
    Ker, MD
    ;
    Lin, KH
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The holding voltage of the high-voltage devices in snapback breakdown condition has been found to be much smaller than the power supply voltage. Such characteristics will cause the LCD driver ICs to be susceptible to the latchup-like danger in the practical system applications, especially while these devices are used in the power-rail ESD clamp circuit. A new latchup-free design on the power-rail ESD clamp circuit with stacked-field-oxide structure is proposed and successfully verified in a 0.25-mu m 40-V CMOS process to achieve the desired ESD level. The total holding voltage of the stacked-field-oxide structure in snapback breakdown condition can be larger than the power supply voltage. Therefore, latchup or latchup-like issues can be avoided by stacked-field-oxide structures for the IC applications with power supply of 40 V.
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    Physical mechanism and device simulation on transient-induced latchup in CMOS ICs under system-level ESD test
    (2005-08-01)
    Ker, MD
    ;
    Hsu, SF
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The physical mechanism of transient-induced latchup (TLU) in CMOS ICs under the system-level electrostatic discharge (ESD) test is clearly characterized by device simulation and experimental verification in time domain. For TLU characterization, an underdamped sinusoidal voltage stimulus has been clarified as the realistic TLU-triggering stimulus under the system-level ESD test. The specific "sweep-back" current caused by the minority carriers stored within the parasitic pnpn structure of CMOS ICs has been qualitatively proved to be the major cause of TLU. All the simulation results on TLU have been practically verified in silicon with test chips fabricated by 0.25-mu m CMOS technology.
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    Evaluation on board-level noise filter networks to suppress transient-induced latchup in CMOS ICs under system-level ESD test
    (2006-02-01)
    Ker, MD
    ;
    Hsu, SF
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Different types of board-level noise filter networks are evaluated to find their effectiveness for improving the immunity of CMOS ICs against the transient-induced latchup (TLU) under the system-level electrostatic discharge (ESD) test. By choosing proper components in each noise filter network, the TLU immunity of CMOS ICs can be greatly improved. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structures and the ring oscillator circuit fabricated in a 0.25-mu m CMOS technology. Some board-level solutions can be further integrated into the chip design to effectively improve the TLU immunity of CMOS IC products.