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A 13.56 MHZ METAMATERIAL FOR THE WIRELESS POWER TRANSMISSION ENHANCEMENT IN IMPLANTABLE BIOMEDICAL DEVICES
(2019-01-01)
Chen, Kuan-Jung
;
Chen, Wei-Ming
;
Tan, Li-Yang
;
Cheng, Yu-Ting
;
Ker, Ming-Dou
This paper presents a 13.56MHz metamaterial for wireless power transmission (WPT) enhancement in implantable biomedical devices based on the evanescent wave coupling mechanism. The power transmission efficiency (PTE) will increase from 46 to 51% with the metamaterial while the transmitting and receiving antennas are placed with a 1 cm distance and lcm offset horizontal misalignment, will increase from 39 to 46% with the metamaterial while the two antenna planes are placed at a distance of 1.5 cm with an axial offset of 15, and will increase from 28 to 50% with two pieces of metamaterial placed with a 0.5cm distance while the two antenna planes are placed with a 1.5 cm distance and 1 cm offset horizontal misalignment.
Design and In Vivo Verification of a CMOS Bone-Guided Cochlear Implant Microsystem
(2019-11-01)
Qian, Xin-Hong
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Wu, Yi-Chung
;
Yang, Tzu-Yi
;
Cheng, Cheng-Hsiang
;
Chu, Hsing-Chien
Objective: To develop and verify a CMOS bone-guided cochlear implant (BGCI) microsystem with electrodes placed on the bone surface of the cochlea and the outside of round window for treating high-frequency hearing loss. Methods: The BGCI microsystem consists of an external unit and an implanted unit. The external system-on-chip is designed to process acoustic signals through an acquisition circuit and an acoustic DSP processor to generate stimulation patterns and commands that are transmitted to the implanted unit through a 13.56 MHz wireless power and bidirectional data telemetry. In the wireless power telemetry, a voltage doubler/tripler (2X/3X) active rectifier is used to enhance the power conversion efficiency and generate 2 and 3 V output voltages. In the wireless data telemetry, phase-locked loop based binary phase-shift keying and load-shift keying modulators/demodulators are adopted for the downlink and uplink data through high-Q coils, respectively. The implanted chip with four-channel high-voltage-tolerant stimulator generates biphasic stimulation currents up to 800 mu A. Results: Electrical tests on the fabricated BGCI microsystem have been performed to verify the chip functions. The in vivo animal tests in guinea pigs have shown the evoked third wave of electrically evoked auditory brainstem response waveforms. It is verified that auditory nerves can be successfully stimulated and acoustic hearing can be partially preserved. Conclusion and Significance: Different from traditional cochlear implants, the proposed BGCI microsystem is less invasive, preserves partially acoustic hearing, and provides an effective alternative for treating high-frequency hearing loss.
On-chip Transient Detection Circuit for Microelectronic Systems against Electrical Transient Disturbances due to ESD Events
(2018-01-01)
Chen, Wen-Chieh
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new on-chip transient detection circuit which can detect electrical disturbances of system-level electrostatic discharge (ESD) is proposed. The circuit is designed with reduced physical area by utilizing dual-latched structure. With hardware/firmware co-design method, auto-recovery procedure can be activated by the detection circuit when microelectronic systems suffer system-level ESD events. The immunity level of microelectronic products against the electromagnetic interference (EMI) of ESD events can be effectively improved. The proposed on-chip transient detection circuit has been verified in a 0.18-mu m CMOS process with 1.8-V devices under system-level ESD tests.
ESD Protection Design of High-Linearity SPDT CMOS T/R Switch for Cellular Applications
(2019-01-01)
Hung, Tao-Yi
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
Electrostatic discharge (ESD) protection design for high-linearity single-pole double-throw (SPDT) transmit/receive switch (T/R switch) at 0.9/1.8 GHz GSM band was proposed and verified in a standard 0.18-mu m CMOS process. The SPDT CMOS T/R switch was implemented with body-floating technique, multi-stacked structure, and series-shunt topology to obtain low insertion loss, high power handling capability, and good isolation. With the proposed ESD protection design, the T/R switch can sustain human-body-model (HBM) ESD voltages of 3.5 kV under the posith e-to-V-ss stress and 5 kV under the negative-to-V-ss stress. Experimental results including ESD characteristics, RF performance, and failure analysis are presented.
An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
(2019-09-01)
Luo, Zhicong
;
Yu, Li-Chin
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A wide-output, power-efficient, high-voltage charge pump with a variable number of stages is proposed and realized in a 0.18 mu m 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage (V-DD). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3-12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.
An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS
(2019-05-01)
Liu, Chi-Wei
;
Chen, Yi-Lun
;
Liao, Pei-Chun
;
Lin, Shiau-Pin
;
Wang, Ting-Wei
This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.
Study and Verification on the Latch-Up Path Between I/O pMOS and N-Type Decoupling Capacitors in 0.18-mu m CMOS Technology
(2019-06-01)
Chen, Chun-Cheng
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
On-chip decoupling capacitors often formed by varactor or nMOS have been widely used to shunt the power-line noise in integrated-circuit products. Because the N+ cathode of these capacitors is connected to ground, an unexpected latch-up path between I/O pMOS and n-type decoupling capacitors may be accidentally triggered on. In this paper, the non-typical latchup path between I/O pMOS and n-type decoupling capacitors was investigated in 0.18-mu m 1.8/3.3-V CMOS technology. The measurement results from the silicon chip with split test structures have verified that the n-type decoupling capacitor near the I/O pMOS can cause a high risk of latch-up. Therefore, the layout rules between the decoupling capacitor and I/O devices should be carefully defined to prevent the occurrence of such an unexpected latch-up path.
Area-Efficient On-Chip Transient Detection Circuit for System-Level ESD Protection Against Transient-Induced Malfunction
(2019-06-01)
Chen, Wen-Chieh
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A new on-chip transient detection circuit with superior area efficiency is proposed against the system malfunction resulting from system-level electrostatic discharge ( ESD) events. With dual-latched structure, a better area efficiency can be achieved by the reduced time constant inquiry. The proposed transient detection circuit with a silicon area of 40 mu m x 60 mu m has been fabricated in a 0.18-mu m CMOS process with 1.8-V devices. The detection sensitivity has been successfully verified under +/- 200 V system-level ESD tests. To achieve the "Class B" specification of IEC 61000-4-2 standard, the proposed transient detection circuit serves as a safety guard for the system. Through the hardware/firmware co-design, the auto-recovery procedure can be activated by the proposed transient detection circuit sending out a warning signal. With the proposed transient detection circuit co-works with the system program, the immunity level of microelectronic products against the electromagnetic compatibility (EMC) of ESD events can be effectively improved.
ESD Protection Design With Diode-Triggered Quad-SCR for Separated Power Domains
(2019-06-01)
Chen, Jie-Ting
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To effectively protect the interface circuit between separated power domains from electrostatic discharge (ESD) damage, a new diode-triggered quad-silicon-controlled rectifier (DTQSCR) is proposed and realized in a 0.18-mu m 1.8-V/3.3-V CMOS process. Since the DTQSCR embeds four silicon-controlled rectifier paths and a structure of back-to-back diodes, the silicon area can be efficiently reduced more than 30% as compared to the traditional ESD protection design under the same ESD specification. From the measurement results in silicon chip, an interface circuit (level shifter) with the proposed ESD protection design can successfully sustain a human-body-model of greater than 5.5 kV. The proposed ESD protection device is suitable to protect the interface circuits between different power domains.
Avalanche Ruggedness Capability and Improvement of 5-V n-Channel Large-Array MOSFET in BCD Process
(2019-07-01)
Nidhi, Karuna
;
Ker, Ming-Dou
;
Lee, Jian-Hsing
;
Huang, Shao-Chang
;
交大名義發表
Energy handling capability of large-array devices (LADs) is one of the most dominating concerns for the designers that affect the device design and its reliability. In this paper, the improvement of the avalanche ruggedness capability by using an optional implantation layer has been investigated the first time for the application of 5-V n-channel large-array MOSFET in a bipolar-CMOS-DMOS (BCD) process. Experimental results with extensive measurements verified that the maximum avalanche current (I-AV) achieved from themodified device is enhanced by more than twice. Moreover, the energy in avalanche single pulse (EAS) capability is improved by more than five times. A significant improvement is noticed in the avalanche safe-operating-area (A-SOA) as compared to the original device, and the failure analysis is discussed in detail. In addition, the impact of an optional implantation layer on the total gate charge (Qg) is also compared for a LAD with a total width of 12 000 mu m.

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