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Author: search.filters.author.Ker, Ming-DouSubject: search.filters.subject.charge pump

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    An Efficient, Wide-Output, High-Voltage Charge Pump With a Stage Selection Circuit Realized in a Low-Voltage CMOS Process
    (2019-09-01)
    Luo, Zhicong
    ;
    Yu, Li-Chin
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A wide-output, power-efficient, high-voltage charge pump with a variable number of stages is proposed and realized in a 0.18 mu m 1.8 V/3.3 V CMOS process. The proposed stage selection circuit changes the node voltages in the charge pump circuit in a domino effect to ensure that the maximum voltages across the terminals of each transistor are kept within the normal supply voltage (V-DD). The stage selection circuit is able to bypass or activate each stage of the charge pump. Experimental results indicate that the proposed charge pump provides a wide-output voltage range: 3.3-12.6 V from a 3.3 V input source. A peak efficiency of 70% was reached in the charge pump at a current loading of 3.5 mA. By selecting the optimal number of active stages, the overall power efficiencies can be greater than 60% under the output voltages of 4.8 V, 8.1 V, and 10.8 V, respectively. By optimizing the number of active stages, an increase of up to 35% power efficiency can be gained. The proposed stage selection circuit is applicable to other on-chip wide-output charge-pumps.
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    An 82.9%-Efficiency Triple-Output Battery Management Unit for Implantable Neuron Stimulator in 180-nm Standard CMOS
    (2019-05-01)
    Liu, Chi-Wei
    ;
    Chen, Yi-Lun
    ;
    Liao, Pei-Chun
    ;
    Lin, Shiau-Pin
    ;
    Wang, Ting-Wei
    This brief presents a high-efficiency battery management unit combining a single-inductor dual-output (SIDO) buck converter with two charge pumps (CPs) to provide three voltage levels (6 V, -6 V, and 2 V) for neuron stimulators in implantable medical devices. The stacked power stage in the buck converter mitigates the voltage stress issue in the power stage to manage 3.2-4.8 V battery voltage. By cascading a buck converter and CPs, the voltage across the CP power stage is reduced to generate 6 V and -6 V high voltage outputs without using high voltage devices. As a result, the proposed battery management could provide 6 V, -6 V, and 2 V output voltages from 3.2 to 4.8 V input voltage using a 180-nm standard CMOS process. The measurement results demonstrate that the proposed battery management achieved a peak efficiency of 82.9% with an available input voltage of 3.2-4.8 V.
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    A High-Voltage-Tolerant and Power-Efficient Stimulator With Adaptive Power Supply Realized in Low-Voltage CMOS Process for Implantable Biomedical Applications
    (2018-06-01)
    Luo, Zhicong
    ;
    Ker, Ming-Dou
    ;
    電子工程學系及電子研究所
    ;
    生醫電子轉譯研究中心
    ;
    Department of Electronics Engineering and Institute of Electronics
    A high-voltage-tolerant and power-efficient stimulator with adaptive power supply is proposed and realized in a 0.18- mu m 1.8-V/3.3-V CMOS process. The self-adaption bias technique and stacked MOS configuration are used to prevent issues of electrical overstress and gate-oxide reliability in low-voltage transistors. The on-chip high-voltage generator uses a pulse-skip regulation scheme to generate a variable dc supply voltage for the stimulator by detecting the headroom voltage on the electrode sites. With a dc input voltage of 3.3 V, the onchip high-voltage generator provides an adjustable dc output voltage from 6.7 to 12.3 V at a step of 0.8 V, which results in a maximal system power efficiency of 56% at a 2400-mu A stimulus current. The charge mismatch of the stimulator is down to 1.7% in the whole stimulus current range of 200-3000 mu A. The in vivo experiments verified that epileptic seizures could be suppressed by the electrical stimulation provided by the proposed stimulator. In addition, the reliability measurements verified that the proposed stimulator is robust for electrical stimulation in medical applications.