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A 94 GHz 10.8 mW Low-Noise Amplifier With Inductive Gain Boosting in 40 nm Digital CMOS Technology
(2019-01-01)
Yeh, Po-Chen
;
Kuo, Chien-Nan
;
交大名義發表
;
National Chiao Tung University
A W-band low-power, low-noise amplifier is designed and fabricated in 40 nm digital CMOS technology. The method of inductive gain boosting is utilized without extra power consumption. The circuit only consumes 10.8 mW dc power with a supply voltage of 1 V. The measured peak power gain achieves 14.5 dB at 93 GHz, while the minimum noise figure is 6.4 dB at 89 GHz. The circuit occupies a core area of only 0.07 mm(2).
A 19.1% PAE, 22.4-dBm 53-GHz Parallel Power Combining Power Amplifier with Stacked-FET Techniques in 90-nm CMOS
(2019-01-01)
Sun, Wei-Che
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A two-stage fully integrated 53-GHz stacked-FET power amplifier (PA) is implemented in 90-nm bulk CMOS. The output stage is optimized to achieve high output power while maintaining high power added efficiency (PAE). The complete PA achieves a measured saturated output power of 22.4 dBm and the 19.1% PAE at 2.4 V supply. It has -3 dB bandwidth of 8.8 GHz.
A W-Band 6.8 mW Low-Noise Amplifier in 90 nm CMOS Technology Using Noise Measure
(2019-01-01)
Yeh, Po-Chen
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A W-band low-noise amplifier consisting of seven common-source transistor stages is designed using noise measure as the figure of merit for circuit optimization. Fabricated in 90 nm CMOS technology, the die size is 0.38 mm(2), while the core active area only 0.1 mm(2). The circuit gives peak power gain of 21.5 dB at 90 GHz and noise figure of 8.3 dB, with dc power consumption of only 6.8 mW.
Enhancement of CMOS THz Imaging Sensing By Packaging Technology
(2017-01-01)
Kuo, Chien-Nan
;
Chen, Wei-Cheng
;
Chiu, Te-Yen
;
Li, Chun-Hsing
;
電子工程學系及電子研究所
Terahertz imaging sensing provides numerous attractive applications in different areas, for example, biology and medicine. CMOS technology benefits an imaging system in low cost and a small form factor. The technology advance is technically viable for circuit design in such high frequencies. Lossy silicon substrate, however, still degrades system performance. We will discuss the techniques of performance enhancement.
Low-Cost High-Performance CMOS Terahertz Imaging System
(2015)
Li, Chung Hsing
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Yan, Tzu-Chao
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Chang, Yuhsin
;
Chen, Chyong
;
Kuo, Chien-Nan
CMOS technology has found its way in THz imaging applications. Utilizing the plasma wave theory, a MOSFET device can detect THz radiation beyond the cutoff frequency. Assisted by the system-on-packaging technique, a CMOS source delivers radiation power more effectively. An imaging system demonstrates that a low-cost CMOS solution is feasible.
The Experimental Study of THz Image Sensor in 0.18 mu m CMOS Technology
(2014)
Lai, Chih-Wei
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Chen, Wei-Cheng
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Yan, Tzu-Chao
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Li, Chun-Hsing
;
Kuo, Chien-Nan
In this study, four different types of power detectors are implemented in 0.18 mu m CMOS technology for the THz image sensor application. These power detectors include common-source with and without supply voltage, and common gate with and without supply voltage. The measured responsivities at 332 GHz are 632 kV/W, 13.2 kV/W, 16.2 kV/W, and 9.1 kV/W, respectively. The image resolution of the proposed THz sensor is 2 mm.
CMOS THz Transmissive Imaging System
(2014)
Yan, Tzu-Chao
;
Li, Chun-Hsing
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Chao, Tzu-Yuan
This paper presents a THz imaging system composed of a signal source and a signal sensor in CMOS technology The signal source integrates a 338 GHz oscillator in 40-nm CMOS and an antenna array on a Benzocyclobutene (BCB) carrier using the SoP (System-on-Package) technique. The measured EIRP achieves +8 dBm. The signal sensor is implemented in 0.18 mu m CMOS. The measured maximum responsivity is 632 kV/W at 332 GHz. The signal source and signal sensor consume dc power of 37.5 mW and 7.92 mW, respectively. The resolution of the proposed THz imaging system is 4 mm.
A 340 GHz Triple-Push Oscillator With Differential Output in 40 nm CMOS
(2014-12-01)
Li, Chun-Hsing
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-power triple-push oscillator with differential output is proposed in this letter. By extracting signals from the same current loop, the oscillator can naturally provide differential output without any additional active circuit or passive balun required. Therefore, the output power can be increased and the chip area and power consumption can be reduced. Realized in 40 nm CMOS technology, the proposed oscillator can oscillate at 340.6 GHz while providing equivalent isotropically radiated power (EIRP) as -21.8 dBm. The power consumption is only 34.1 mW from a 0.9 V supply. The oscillator core only occupies area of 0.028 mm(2).
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
;
Chao, Tzu-Yuan
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.
A 1.2-V 5.2-mW 20-30-GHz Wideband Receiver Front-End in 0.18-mu m CMOS
(2012-11-01)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper presents a low-power wideband receiver front-end design using a resonator coupling technique. Inductively coupled resonators, composed of an on-chip transformer and parasitic capacitances from a low-noise amplifier, a mixer, and the transformer itself, not only provide wideband signal transfer, but also realize wideband high-to-low impedance transformation. The coupled resonators also function as a wideband balun to give single-to-differential conversion. Analytic expressions for the coupled resonators with asymmetric loads are presented for design guidelines. The proposed receiver front-end only needs a few passive components so that gain degradation caused by the passive loss is minimized. Hence, power consumption and chip area can be greatly reduced. The chip is implemented in 0.18-mu m CMOS technology. The experimental result shows that the -3-dB bandwidth can span from 20 to 30 GHz with a peak conversion gain of 18.7 dB. The measured input return loss and third-order intercept point are better than 16.7 dB and -7.6 dBm, respectively, over the bandwidth. The minimum noise figure is 7.1 dB. The power consumption is only 5.2 mW from a 1.2-V supply. The chip area is only 0.18 mm(2).

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