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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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A Low-Cost Broadband Bondwire Interconnect for Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Ko, Chun-Lin
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
A low-cost broadband interconnect, composed of bondwires and transmission lines, is proposed for heterogeneous system integration. By designing the length and the characteristic impedance of the transmission lines, the bondwire effect can be reduced to provide an interconnect with good return loss and low insertion loss. In this work, the chip and the carrier are realized in 90-nm CMOS and GIPD process, respectively. Measured results show that the return loss and the insertion loss are better than 10 dB and 1.1 dB, respectively, from DC to 45.2 GHz.
A Broadband Interconnect for THz Heterogeneous System Integration
(2013)
Li, Chun-Hsing
;
Wu, Jan-Jr
;
Kuo, Chien-Nan
;
Cheng, Yu-Ting
;
Kuo, Ming-Ching
A broadband interconnect for THz heterogeneous system integration is proposed using a resonator coupling technique. Two resonators, deployed on a chip and a carrier, respectively, are coupled through the electromagnetic field to provide a low-loss interconnect in a broadband manner. Simulation results indicate an insertion loss of 0.32 dB at 170 GHz while covering 3-dB bandwidth from 100 to 344 GHz. Measurement can be conducted to verify its performance only from 140 GHz to 220 GHz, due to equipment limit. The measured minimum insertion loss is 0.47 dB at 164 GHz.
A 8-mW 77-GHz Band CMOS LNA by Using Reduced Simultaneous Noise and Impedance Matching Technique
(2015)
Ko, Chun-Lin
;
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
Chang, Da-Chiang
This paper presents analysis and design of source inductance for multistage LNA at 77-GHz band in 90 nm CMOS technology. Instead of simultaneous noise and impedance matching, the analysis shows the optimum degeneration of the single stage design for millimeter-wave frequencies. A low-power 77-GHz band LNA has been demonstrated to verify the optimization result. By using the proposed method, the LNA exhibited a low noise figure of 5.1 dB and a gain of 18.1 dB at 78.5 GHz with only 8 mW from a 1-V power supply.
A 1.3 GHz-5.3 GHz Wideband, High Linearity Balun Low Noise Amplifier
(2011)
Yang, Kai-Hsiang
;
Kuo, Ming-Ching
;
Yan, Tzu-Chao
;
Kuo, Chien-Nan
;
電子工程學系及電子研究所
In this work, a balun low-noise amplifier (LNA) is designed and implemented in 0.18-mu m CMOS process. The bulk cross-coupling (BCC) and capacitance cross-coupling (CCC) techniques are introduced in this LNA, which not only increase gain and linearity but also decrease noise figure. The 3 dB bandwidth extends from 1.27 GHz to 5.31 GHz. The maximum differential gain is 10.13 dB. Measured at 3 GHz, P-1dB and IIP3 are -10 dBm and 0 dBm, respectively. The LNA core circuit dissipates 7.32 mW from 1.8 V power supply.
Constant Excess Bias Control for Single-Photon Avalanche Diode Using Real-Time Breakdown Monitoring
(2015-08-01)
Chang, Po-Hsuan
;
Tsai, Chia-Ming
;
Wu, Jau-Yang
;
Lin, Sheng-Di
;
Kuo, Ming-Ching
A monolithic constant excess bias control circuit for single-photon avalanche diode (SPAD) in standard 0.18-mu m CMOS technology is reported. The proposed real-time breakdown monitoring technique is incorporated into a passive-quenching-active-reset circuit. A sample-and-hold circuit samples the breakdown level of SPAD through well-defined sampling phase. Following the sample-and-hold circuit, the level shifter with voltage shifting defined by predetermined excess bias provides the reset voltage of SPAD. The design operates the SPAD under constant excess bias and effectively mitigates the impact of the process-voltage-temperature variation by maintaining the optimal excess bias condition.
A 37.5-mW 8-dBm-EIRP 15.5 degrees-HPBW 338-GHz Terahertz Transmitter Using SoP Heterogeneous System Integration
(2015-02-01)
Li, Chun-Hsing
;
Chao, Tzu-Yuan
;
Lai, Chih-Wei
;
Chen, Wei-Cheng
;
Ko, Chun-Lin
A low-cost terahertz transmitter is proposed by using system-on-package (SoP) heterogeneous system integration. A signal source in 40-nm CMOS is integrated with an antenna array on a Benzocyclobutene carrier through a broadband low-loss terahertz interconnect. The signal source adopting triple-push oscillator topology is able to produce a differential output without any additional balun circuit. Hence, the power consumption and the chip area can be reduced. The antenna array containing 50 patch antennas is differentially excited to give simulated directivity, efficiency, and antenna gain as high as 22.6 dB, 88%, and 22 dBi, respectively, at 335 GHz. The terahertz interconnect employs a resonator coupling technique to provide low-loss and broadband performance while occupying a small area. Measured results show that the proposed terahertz transmitter can work at 338.4 GHz with equivalent isotropically radiated power (EIRP) of 8.0 dBm while consuming only 37.5 mW from a 1-V supply. The measured half-power beam-width can be as narrow as 15.5 degrees. The EIRP can be further raised to 9.5 dBm as the supply V-DD is increased to 1.3 V. The CMOS chip only occupies an area as small as 0.028 mm(2). All of the design efforts enable the proposed terahertz transmitter to feature in small form factor, low power dissipation, low cost, and high performance. To the best of the authors\' knowledge, this is the most compact, lowest power, lowest cost, and high-performance SoP-based terahertz transmitter reported thus far.
A High Q On-Chip Bondwire Transformer and Its Application to Low Power Receiver Front-End Design
(2013)
Li, Chun-Hsing
;
Kuo, Chien-Nan
;
Kuo, Ming-Ching
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This work presents a high Q on-chip bondwire transformer and its application to a low power receiver front-end design. The proposed bondwire transformer has the advantage of high quality factor, less sensitivity to the bonding height variation, and working as a balun to conduct single-to-differential conversion. Furthermore, the chip area under the bondwire transformer can be reused by the mixer and buffer circuits to reduce the cost. The receiver front-end is realized in 1P6M 0.18 mu m CMOS technology. The measured input return loss, the conversion gain, the noise figure, and the input third-order intercept point are 12.7 dB, 20.5 dB, 9.8 dB, and -4.0 dBm, respectively, at 2.1 GHz. The power consumption is only 1.1 mW from a 1 V supply.

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🏛️國立陽明交通大學機構典藏

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