🏛️國立陽明交通大學機構典藏

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An improved soft-input CAVLC decoder for mobile communication applications
(2006)
Liu, Tsu-Ming
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
in this paper, a new CAVLC decoding architecture with a soft-input design concept is proposed. We introduce the soft-decision information to localize the erroneous position at macroblock (MB) levels. Specifically, we compare and select the minimal square difference between the received soft streams and decoded codewords. The corrupted MBs can be early detected and thereby concealed from neighboring pixels. Therefore, more than 1dB of PSNR gain can be achieved under the 2.7x10(-3) of bit error rates.
Design of a 125 mu W, fully-scalable MPEG-2 and H.264/AVC video decoder for mobile applications
(2006)
Liu, Tsu-Ming
;
Chung, Ching-Che
;
Lee, Chen-Yi
;
Lin, Ting-An
;
Wang, Sheng-Zen
A design of MPEG-2 and H.264/AVC video decoder is demonstrated in a 0.18 mu m CMOS [1]. The key design issues involved in this advanced IC are discussed, including improving area and power efficiency. Power dissipation is greatly lowered through the architectural exploration. Measurement results show that MPEG-2 and H.264/AVC real-time decoding of QCIF@15fps are achieved at 1.15MHz with power dissipation of 108 mu W and 125 mu W respectively at 1V supply voltage.
An in/post-loop deblocking filter with hybrid filtering schedule
(2007-07-01)
Liu, Tsu-Ming
;
Lee, Wen-Ping
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we propose a high-throughput deblocking filter to perform the in-loop or post-loop filtering process for different standard requirements. The performance improvement is very mild if we replace a post-loop filter with an in-loop filter. To alleviate this problem, we derive an integration-oriented algorithm that can be reconfigured as the in-loop or, post-loop filter. Moreover, we develop a hybrid filtering schedule to reach a lower bound of processing cycles. In particular, we reschedule the filtering order and reuse the intermediate pixels when the deblocking filter switches the filtered edges from vertical to horizontal direction. Finally, a 0.18-mu m CMOS design that performs the in/post-loop filter with the hybrid filtering schedule is implemented. The synthesized gate counts are 21.1 K which is reduced to 70% of preliminary design that performs the in-loop or post-loop filter separately. Moreover, it achieves 4 x 10(5) macroblock/s of throughput rate at a 100-MHz clock rate.
Design of an H.264/AVC decoder with memory hierarchy and line-pixel-lookahead
(2008-01-01)
Liu, Tsu-Ming
;
Lee, Chen-Yi
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
This paper describes a novel memory hierarchy and line-pixel-lookahead (LPL) for an H.264/AVC video decoder. The memory system is the bottleneck of most video processors, particularly in the newly announced H.264/AVC. This is because it utilizes the neighboring pixels to create a reliable predictor, leading to a dependency on a long past history of data. This problem can be resolved by allocating memory space but inducing large silicon area and power consumption as well. We first review the existing solutions and propose a three-level memory hierarchy with line-pixel-lookahead to improve access efficiency. Three-level memory hierarchy includes registers, content/slice SRAM and external frame DRAM. We emphasize the need to consider the secondary hierarchy, content/slice SRAM, during the design of an H.264/AVC decoder. Specifically, we introduce a slice SRAM and line-pixel-lookahead to lower the memory capacity and external bandwidth. This SRAM stores neighboring pixels and prevents the data re-access from DRAM. Line-pixel-lookahead exploits multi-dimensional pixel locality so as to averagely improve prediction performance by 6.54% compared to conventional vertical prediction. Simulation results also reveal that the proposal makes a better trade-off between memory allocation and external bandwidth as well as power, leading to 50% of memory power reduction compared to the design without exploiting the secondary slice SRAM hierarchy.
A 125 mu W, fully scalable MPEG-2 and H.264/AVC video decoder for mobile applications
(2007-01-01)
Liu, Tsu-Ming
;
Lin, Ting-An
;
Wang, Sheng-Zen
;
Lee, Wen-Ping
;
Yang, Jiun-Yan
A low-power dual-standard video decoder has been developed for mobile applications. It supports MPEG-2 SP@ML and H.264/AVC BL@L4 video decoding in a single chip and features a scalable architecture to reach area/power efficiency. This chip integrates diverse algorithms of MPEG-2 and H.264/AVC to reduce silicon area. Three low-power techniques are proposed. First, a domain-pipelined scalability (DPS) technique is used to optimize the pipelined structure according to the number of processing cycles. Second, bandwidth scalability is implemented via a line-pixel-lookahead (LPL) scheme to improve the external bandwidth and reduce the internal memory size, leading to 51% of memory power reduction compared to a conventional design. Third, low-power motion compensation and deblocking filter are designed to reduce the operating frequency without degrading system performance. A test chip is fabricated in a 0.18 mu m one-poly six=metal CMOS technology with an area of 15.21 mm(2). For mobile applications, H.264/AVC and MPEG-2 video decoding of quarter-common intermediate format (QCIF) sequences at 15 frames per second are achieved at 1.15 MHz clock frequency with power dissipation of 125 mu W and 108 mu W, respectively, at 1 V supply voltage.

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🏛️國立陽明交通大學機構典藏

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