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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作,涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.
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Item type:Item, An OFDM-based 29.1Mbps 0.22nJ/bit Body Channel Communication Baseband Transceiver(2015) ;Tsai, Ping-Yuan ;Chang, Yu-Yun ;Hsu, Shu-Yu ;Lee, Chen-Yi電機學院This paper proposes an energy-efficient transceiver for body channel communication. 16-QAM OFDM is adopted to enhance the data rate and ( 2,1,6) convolutional code is integrated to remain the transmission reliability, where the hard-decision Viterbi Decoder gives the coding gain by 2dB. The modulator of the transceiver provides two modes -high speed mode and low power mode. In the low power mode an uneven multi-level LINC architecture is adopted. The average-power based auto gain control is applied in the receiver to ensure the transmission quality under different paste distances and different users. The chip is implemented under 90nm CMOS technology with 5.2 mm(2) chip area. The data rate achieves 29.1Mbps with 6.349 mW power dissipation, resulting in 0.22nJ/b bit per energy.Item type:Item, A Sub-mW All-Digital Signal Component Separator With Branch Mismatch Compensation for OFDM LINC Transmitters(2011-11-01) ;Chen, Tsan-Wen ;Tsai, Ping-Yuan ;Yu, Jui-Yuan ;Lee, Chen-Yi電機工程學系Linear amplification with nonlinear components (LINC) is an attractive technique for achieving linear amplification with high efficiency. This paper presents a sub-mW all-digital signal component separator (SCS) design for OFDM LINC transmitters, including a phase calculator and a digital-control phase shifter (DCPS) pair. In addition, a digital mismatch compensation scheme is proposed and integrated into the SCS to reduce the design complexity of the power amplifier. This chip is manufactured in a 90 nm standard CMOS process with an active area of 0.06 mm(2). The DCPS can generate phase-modulated signals at 100 MHz with 8-bit resolution and RMS error 9.33 ps (0.34 degrees). The phase calculation can be performed at a maximum speed of 50 MHz using a 0.5 V supply voltage, resulting in a 73.88% power reduction. Comparing to state-of-the-art, the power consumption of the overall SCS is only 949.5 mu W which minimizes the power overhead for an LINC transmitter. This SCS with the branch mismatch compensation provides a 0.02 dB gain and 0.15 degrees phase fine-tune resolution without adding additional front-end circuits. Considering 1 dB gain and 10 degrees phase mismatch, the system EVM of -29.81 dB and ACPR of -34.56 dB can still be achieved for 5 MHz bandwidth 64-QAM OFDM signals.Item type:Item, A Synchronization Method for Crystal-Less OFDM-Based Wireless Body Area Network Applications(2009) ;Ma, Hsiao-Han ;Yu, Chien-Ying ;Yu, Jui-Yuan ;Lee, Chen-Yi電子工程學系及電子研究所A synchronization method includes packet detection and frequency error estimation (PAFEE) is proposed for crystal-less OFDM-based wireless body area network (WBAN) applications to enlarge the frequency error tolerance between the transmitter and receiver. The packet detection method is designed to overcome the large frequency error. The estimated frequency offset (FO) value is provided to a crystal-less tunable clock source. The evaluation platform is the eCrystal WiBoC OFDM-based system. The system overall frequency error tolerance is extended 140x of existing wireless systems. The system is designed and simulated in a 90nm technology with 148.5 mu W computation power and 0.06mm(2) area overhead. Comparing to quartz crystal systems, the overall power reduction is 89.3%, and area reduction is 98.4%.Item type:Item, A dynamic phase-frequency recovery for power reduction in OFDM systems(2007) ;Yang, Mei-Hui ;Yu, Jui-Yuan ;Chen, Juinn-Ting ;Lee, Chen-Yi電子工程學系及電子研究所A dynamic phase and frequency recovery (DPR & DFR) is proposed for power reduction and performance improvement. By the DPR, signal sampling rate is reduced from Nyquist rate (or higher) to the symbol rate, resulting in reduced ADC circuit power. By the DFR, data is recovered from less-interfered signals. In the MB-OFDM UWB system, the simulations show that the system improves 2.3 dB SNR and reduce 43.75% ADC power consumption with the proposed techniques.