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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Lee, Chen-YiSubject: search.filters.subject.machine learning

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Now showing 1 - 3 of 3
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    A 41.3pJ/26.7pJ Per Neuron Weight RBM Processor for on-Chip Learning/Inference Applications
    (2016-01-01)
    Tsai, Chang-Hung
    ;
    YU, Wan-Jun
    ;
    Wong, Wing Hung
    ;
    Lee, Chen-Yi
    ;
    電子工程學系及電子研究所
    A restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning applications in this paper. Featuring neural network (NN) model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism in learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology', the proposed RBM-P chip costs 2.2M gates and 128kB SRAM with 8.8mm(2) area. Operated at 1.2V and 210MHz, this chip respectively achieves 114.3x and 3.9x faster processing time than CPU and GPGPU. And the proposed RBM-P chip consumes 41.3pJ and 26.7pJ per neuron weight (NW) for learning and inference, respectively.
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    A 41.3/26.7 pJ per Neuron Weight RBM Processor Supporting On-Chip Learning/Inference for IoT Applications
    (2017-10-01)
    Tsai, Chang-Hung
    ;
    Yu, Wan-Ju
    ;
    Wong, Wing Hung
    ;
    Lee, Chen-Yi
    ;
    電子工程學系及電子研究所
    An energy-efficient restricted Boltzmann machine (RBM) processor (RBM-P) supporting on-chip learning and inference is proposed for machine learning and Internet of Things (IoT) applications in this paper. To train a neural network (NN) model, the RBM structure is applied to supervised and unsupervised learning, and a multi-layer NN can be constructed and initialized by stacking multiple RBMs. Featuring NN model reduction for external memory bandwidth saving, low power neuron binarizer (LPNB) with dynamic clock gating and area-efficient NN-like activation function calculators for power reduction, user-defined connection map (UDCM) for both computation time and bandwidth saving, and early stopping (ES) mechanism for learning process, the proposed system integrates 32 RBM cores with maximal 4k neurons per layer and 128 candidates per sample for machine learning applications. Implemented in 65nm CMOS technology, the proposed RBM-P chip costs 2.2 M gates and 128 kB SRAM with 8.8 mm(2) area. Operated at 1.2 V and 210 MHz, this chip achieves 7.53G neuron weights (NWs) and 11.63G NWs per second with 41.3 and 26.7 pJ per NW for learning and inference, respectively.
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    A 48.6-to-105.2 mu W Machine Learning Assisted Cardiac Sensor SoC for Mobile Healthcare Applications
    (2014-04-01)
    Hsu, Shu-Yu
    ;
    Ho, Yingchieh
    ;
    Chang, Po-Yao
    ;
    Su, Chauchin
    ;
    Lee, Chen-Yi
    A machine- learning ( ML) assisted cardiac sensor SoC ( CS- SoC) is designed for mobile healthcare applications. The heterogeneous architecture realizes the cardiac signal acquisition, filtering with versatile feature extractions and classifications, and enables the higher order analysis over traditional DSPs. Besides, the asynchronous architecture with dynamic standby controller further suppresses the system active duty and the leakage power dissipation. The proposed chip is fabricated in a 90- nm standard CMOS technology and operates at 0.5 V- 1.0 V ( 0.7 V- 1.0 V for SRAM and I/ O interface). Examined with healthcare monitoring applications, the CS- SoC dissipates 48.6/ 105.2 mu W for real- time syndrome detections of ECG- based arrhythmia/ VCG- based myocardial infarction with 95.8/ 99% detection accuracy, respectively.