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A novel structure for three-dimensional silicon magnetic transducers to improve the sensitivity symmetry
(1996-09-01)
Lin, HY
;
Lei, TF
;
Jeng, JJ
;
Pan, CL
;
Chang, CY
A three-dimensional silicon magnetic transducer with symmetric sensitivities in the x-, y- and z-directions and small cross sensitivity has been demonstrated. Devices are based on a design of a vertical Hall structure using the surrounding trench and symmetric design to suppress the cross sensitivity. The fabrication process is simple and can be used as a part of a standard integrated circuit process. The results show that almost equal sensitivities in all three components of magnetic field can be obtained by coating Ni/Co thin films on the backside of the substrates. The cross sensitivity is only 1.3% of the sensitivity.
Suppression of boron penetration in BF2+-implanted poly-Si gate
(1996-12-01)
Chao, TS
;
Chu, CH
;
Wang, CF
;
Ho, KJ
;
Lei, TF
In this paper, a comprehensive study of gate engineering to suppress the penetration of boron in p-type metaloxide-semiconductor held-effect transistor (MOSFET) with the p(+)-poly-Si-gate is reported. Four types of poly-Si gate structure, two types of gate dielectrics were investigated to suppress the boron penetration. Among the different gate structures, the stacked amorphous silicon structure was found to be the most effective way to retard the boron penetration. N2O oxide exhibited a better retarding of the boron diffusion as compared with the O-2 oxide. It was found that a combination of stacked amorphous silicon with N2O oxide is the most effective way to suppress the boron penetration. Thermal stability, oxide integrity, and D-it of this sample are superior to all the other samples.
MOS magnetic current sensor based on standard CMOS process
(1997-03-27)
Yang, HM
;
Lei, TF
;
Huang, YC
;
Lee, CL
;
電子工程學系及電子研究所
A novel current sensor is proposed. The current sensor consists of one MOS magnetic sensor and a flat coil in an industrial CMOS process, An experimental device demonstrated a sensitivity of 8.4mV/A.
Improvement of water-related hot-carrier reliability by optimizing the plasma-enhanced tetra-ethoxysilane deposition process
(1997-08-01)
Lin, YM
;
Jang, SM
;
Yu, CH
;
Lei, TF
;
電子工程學系及電子研究所
As-deposited, steam-exposed O-3-tetra-ethoxysilane (TEOS)-based intermetallic dielectric were characterized according to the LR-absorption spectra. The plasma-enhanced-TEOS films investigated here were formed by mixed-frequency plasma processes and differentiated by reaction oxidizers and/or plasma powers. Increasing stress and nitrogen or oxygen concentrations improved the moisture resistance of PE-TEOS oxide films. In addition to the moisture resistance of PE-TEOS films, another factor affecting hot-carrier robustness is the maximum thickness of the underlayer for O-3-TEOS films, which is limited by their conformity The integrated intermetallic dielectrics were evaluated by constant-current and hot-carrier stressing. In obtaining the best device reliability, a trade-off exists between moisture resistance, gapfilling capacity of the PE-TEOS underlayer, and plasma damage. Our results indicate that an O-2-rich, PE-TEOS film with a mechanical stress of 3 x 10(9) dyn/cm(2) is the optimum.
Monitoring trapped charge generation for gate oxide under stress
(1997-09-01)
Lin, YH
;
Lee, CL
;
Lei, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A measurement method to extract the respective quantities and centroids of positive and negative trapped charges, i.e., Q(p) and Q(n), generated by the negative current stress for gate oxides is proposed and demonstrated, The method is based on neutralization of Q(p) by a low positive current stress to differentiate the effects of Q(p) and Q(n). From the extracted quantities and centroids of Q(p) and Q(n) of negatively stressed oxides, it was found that Q(p) and Q(n) are generated near the oxide/substrate interface and Q(p) is initially much larger than Q(n). After the continuous stressing, Q(p) saturates and moves closer to the interface, but Q(n) keeps increasing and moves away from the interface, especially for those oxides after the post-poly anneal (PPA) treatment, Q(n) is very unstable and easily neutralized, either by a small stress of opposite polarity or the same polarity, For the latter, Q(n) is mainly dependent on the level of the final stressing field.
Plasma charging damage and water-related hot-carrier reliability in the deposition of plasma-enhanced tetraethylorthosilicate oxide
(1997-07-01)
Lin, YM
;
Jang, SM
;
Yu, CH
;
Lei, TF
;
Chen, JY
This paper presents plasma-enhanced tetraethylorthosilicate oxide process (PETEOS) induced hot-carrier reliability associated with an intermetallic dielectric formed by depositing oxide films from PETEOS, ozone-TEOS, and spin-on glass (SOG), where a single or dual-frequency PETEOS film is deposited as an underlayer followed by an ozone-TEOS deposition for gap filling and a SOG coating for planarization. The impact of PETEOS process conditions such as low-and high-frequency plasma power and PETEOS film thickness on hot-carrier reliability are studied. It is observed that increasing the low- and/or high-frequency plasma power can improve the film quality and moisture-related hot carrier immunity, but at the expense of plasma charging damage. This plasma charging damage accumulates gradually and finally saturates as the deposition of oxide from PETEOS proceeds. In general, a thick PETEOS layer is desired for improving the moisture-related hot carrier immunity. As a result, there is a trade-off between the plasma charging damage and the moisture-related hot carrier immunity. The plasma charging damage is dominant in large devices and the moisture-related hot-carrier immunity is dominant in small devices.
Improvement of reliability of metal-oxide semiconductor field-effect transistors with N2O nitrided gate oxide and N2O polysilicon gate reoxidation
(1998-10-01)
Lai, CS
;
Chao, TS
;
Lei, TF
;
Lee, CL
;
Huang, TY
A systematic study of the impact of the reliability of metal-oxide semiconductor field-effect transistors (MOSFETs) with N2O nitrided gate oxides and N2O poly-reoxidation was conducted. The improvements include hot carrier immunity, suppression of reverse short channel effect and suppression of plasma-induced degradation. These improvements are due to nitrogen incorporation at the oxide/Si-substrate interface. All data presented in this study involve substantially low thermal budget (850 degrees C), making this N2O-related technology extremely attractive and promising for future scaled devices.
Correlation of stress-induced leakage current with generated positive trapped charges for ultrathin gate oxide
(1998-02-01)
Lin, YH
;
Lee, CL
;
Lei, TF
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this work, the evidence of the stress-induced leakage current related with the stress-generated positive trapped charges is presented and investigated. It is shown that the centroid of the positive trapped charges, which depends on the polarity of the stress current, affects the magnitude of the leakage current. And the trapping density of positive charges, which is determined by the final stress applied on the oxide, determines the final level of the leakage currents.
Mechanism of nitrogen coimplant for suppressing boron penetration in p(+)-polycrystalline silicon gate of p metal-oxide semiconductor field effect transistor
(1996-09-16)
Chao, TS
;
Liaw, MC
;
Chu, CH
;
Chang, CY
;
Chien, CH
The mechanism of the nitrogen co-implant to suppress the boron penetration in p(+)-polycrystalline silicon gate has been investigated. The nitrogen coimplant with the BF, combines with the boron to form a B-N complex which results in a retardation of boron diffusion. It is found that metal-oxide-silicon capacitors with nitrogen implantation show improved electrical properties. (C) 1996 American Institute of Physics.
Low-temperature and low thermal budget fabrication of polycrystalline silicon thin-film transistors
(1996-11-01)
Lin, HY
;
Chang, CY
;
Lei, TF
;
Liu, FM
;
Yang, WL
A top-gate self-aligned n-channel polycrystalline silicon (poly-Si) thin-film transistor (TFT) has been fabricated with low temperature (less than or equal to 550 degrees C) and low thermal budget process. The ultrahigh vacuum chemical vapor deposition (UHV/CVD) grown poly-Si was served as the channel film, the chemical mechanical polishing (CMP) technique was used to polish the channel surface, plasma-enhanced chemical vapor deposited (PECVD) tetraethylorthosilicate (TEOS) oxide was used as the gate dielectric, and NH3 plasma was used to passive the device. In this process, the solid phase crystallization (SPC) step Is not needed. A field effect mobility of 46 cm(2)/V-s, ON/OFF current ratio of over 10(7), and threshold voltage of 0.8 V are obtained. The significant reduction in process temperature and thermal budget make this process advantageous for larger-area-display peripheral driver circuits on glass substrate.

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