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Process-Variation- and Random-Dopant-Induced Static Noise Margin Fluctuation in Nanoscale CMOS and FinFET SRAM Cells
(2009)
Li, Tien-Yeh
;
Hwang, Chih-Hong
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this study, a three-dimensional "atomistic" coupled device-circuit simulation approach is advanced to investigate the process-variation-effect (PVE) and random dopant fluctuation (RDF) induced characteristic fluctuations in planar metal-oxide-semiconductor field-effect-transistor (MOSFET) static random access memory (SRAM) from 65-nm to 16-nm gate length. Our preliminary results show that the RDF dominates the fluctuation of static noise margin (SNM). As the gate length of the planar MOSFETs scales from 65 nm to 16 nm, the normalized RDF-induced SNM fluctuation increases from 4% to 80%. To reduce the device variability induced fluctuation in circuit, a device with vertical-doping-profile and raised V(th) is employed. The SNM is 3 times larger than the original 16-nm-gate SRAM. Moreover, the normalized RDF-induced SNM fluctuation is reduced by a factor of 2.67. Additionally, a 16-nm-gate silicon-on-insulator fin-type field-effect-transistor is used to further improve the SNM of SRAM. Due to the superior electrostatic integrity and larger effective device width than planar MOSFETs, the SNM of 16-nm-gate FinFET SRAM is six times larger than the original 16 nm SRAM with five times smaller SNM fluctuation. The study investigates the roll-off characteristics of SNM and provides an insight into design of fluctuation resistant nanoscale SRAM.
Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit
(2009-05-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
電信工程研究所
;
Institute of Communications Engineering
As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits using a 3-D "atomistic" coupled device-circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 1.6-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.
The geometric effect and programming current reduction in cylindrical-shaped phase change memory
(2009-07-15)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Cheng, Hui-Wen
;
電子工程學系及電子研究所
This study conducts a three-dimensional electro-thermal time-domain simulation for numerical analysis of cylindrical-shaped phase change memories (PCMs). The influence of chalcogenide material, germanium antimony telluride (GeSbTe or GST), structure on PCM operation is explored. GST with vertical structure exhibits promising characteristics. The bottom electrode contact (BEC) is advanced to improve the operation of PCMs, where a 25% reduction of the required programming current is achieved at a cost of 26% reduced resistance ratio. The position of the BEC is then shifted to further improve the performance of PCMs. The required programming current is reduced by a factor of 11, where the resistance ratio is only decreased by 6.9%. However, the PCMs with a larger shift of BEC are sensitive to process variation. To design PCMs with less than 10% programming current variation, PCMs with shifted BEC, where the shifted distance is equal to 1.5 times the BEC's radius, is worth considering. This study quantitatively estimates the structure effect on the phase transition of PCMs and physically provides an insight into the design and technology of PCMs.
Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits
(2009-08-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
電信工程研究所
;
Institute of Communications Engineering
The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function-and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale CMOS field-effect-transistor circuits.
Process-Variation Effect, Metal-Gate Work-Function Fluctuation, and Random-Dopant Fluctuation in Emerging CMOS Technologies
(2010-02-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
傳播研究所
This paper, for the first time, estimates the influences of the intrinsic-parameter fluctuations consisting of metal-gate work-function fluctuation (WKF), process-variation effect (PVE), and random-dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field-effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold-voltage fluctuation (sigma V(th)); however, the WKF brings less impact on the gate capacitance and the cutoff frequency due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the sigma V(th) and is therefore proportional to the trend of sigma V(th). The power fluctuation consisting of the dynamic, short-circuit, and static powers is further investigated. The total power fluctuation for the planar MOSFET circuits is 15.2%, which is substantial in the reliability of circuits and systems. The static power is a minor part of the total power; however, its fluctuation is significant because of the serious fluctuation of the leakage current. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3-dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuit characteristic fluctuations due to the significant gate-capacitance fluctuations, and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can, in turn, be used to optimize nanoscale MOSFETs and circuits.

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