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Now showing 1 - 8 of 8

Novel Metamorphic HEMTs With Highly Doped InGaAs Source/Drain Regions for High Frequency Applications
(2010-10-01)
Sahoo, Kartika Chandra
;
Kuo, Chien-I
;
Li, Yiming
;
Chang, Edward Yi
;
材料科學與工程學系
In this paper, we report the first result of a strained In(0.52)Ga(0.48) As channel high-electron mobility transistor (HEMT) featuring highly doped In(0.4)Ga(0.6) As source/drain (S/D) regions. A lattice mismatch of 0.9% between In(0.52)Ga(0.48) As and In(0.4)Ga(0.6) As S/D has resulted in a lateral strain in the In(0.52)Ga(0.48) As channel region, where the series resistance is reduced with highly doped S/D regions. An experimentally validated device simulation is advanced for the proposed HEMT, and the results of this paper have shown that there are 60% drive-current and 100% transconductance improvements, compared with the conventional structure. A remarkable 150-GHz increase in the cutoff frequency has been seen for the proposed structure over the conventional one as well for the shown devices.
A novel AlGaN/GaN multiple aperture vertical high electron mobility transistor with silicon oxide current blocking layer
(2015-08-01)
Shrestha, Niraj Man
;
Wang, Yuen Yee
;
Li, Yiming
;
Chang, Edward Yi
;
材料科學與工程學系
In this work, a new AlGaN/GaN vertical high electron mobility transistor (HEMT) with silicon oxide (SiO2) current blocking layer (CBL) is designed and studied numerically for high-power devices. To overcome the excessive vertical leakage through CBL layer in conventional p-GaN CBL vertical HEMT, large band-gap material, SiO2 is, for the first time, introduced as a CBL material. The band-gap of SiO2 leads to a large barrier which can effectively suppress the vertical leakage even at high drain bias and enhance the breakdown voltage to 1270 V (154% enhancement compared with the conventional p-GaN CBL vertical HEMT). In addition, a device with four parallel apertures is proposed to reduce the aperture resistance, where the total aperture thickness is equal to the aperture thickness of the conventional one. Therefore, the drain current is increased. We not only focus on the vertical leakage control, but also, on the drain current boost (7% improvement). (c) 2014 Elsevier Ltd. All rights reserved.
Device Simulation of P-InAlN-Gate AlGaN/GaN High Electron Mobility Transistor
(2014-01-01)
Shrestha, Niraj Man
;
Lin, Yueh-Chin
;
Chang, Han-Tung
;
Li, Yiming
;
Chang, Edward Yi
Enhancement mode AlGaN/GaN high electron mobility transistor with p-InAlN gate is designed and successfully studied its electrical properties. Threshold voltage of the device is 1.9 V, which is required magnitude of threshold voltage for real device. Similarly, the maximum drain current is 520 mA/mm and trasconductance is 183 mS/mm, which is the record estimation for enhancement-mode (e-mode) device with recorded threshold voltage. P-InAlN layer injects hole to the barrier at higher gate voltage and results in comparatively larger drain current. Selective area etching and re-grow AlInN causes thin barrier layer beneath the gate. This recess like p-InAlN structure can reduce the concentration of 2DEG; and thus results the high magnitude of threshold voltage.
Capacitance Characteristic Optimization of Germanium MOSFETs with Aluminum Oxide by Using a Semiconductor-Device-Simulation-Based Multi-Objective Evolutionary Algorithm Method
(2015-04-03)
Li, Yiming
;
Chen, Chieh-Yang
;
傳播研究所
;
電機資訊學士班
;
Institute of Communication Studies
This paper, for the first time, optimizes the characteristics of capacitance-voltage (C-V) of germanium (Ge) metal-oxide-semiconductor field effect transistors (MOSFETs) with aluminum oxide (Al2O3) by using a semiconductor-device-simulation-based multi-objective evolutionary algorithm (MOEA) technique. By solving a set of 2D semiconductor device transport equations, numerical simulation is intensively performed for the optimization of the C-V curve of Ge MOSFET devices. To optimize the capacitance of Ge MOSFETs with respect to the applied voltage, by minimizing the total errors of the C-V curve between the device simulation and a given specification (and experimentally measured data), the thicknesses of Al2O3 and GeO2, the work function of gate electrodes, the distribution range of channel doping, the dielectric constants of Al2O3 and GeO2, and the source/drain doping concentration are considered in the process of optimization. The semiconductor device simulation and the MOEA method are integrated and performed based on a unified optimization framework. According to the sharp variation characteristics of the C-V curve, except for using a residual sum of squares (RSS) (i.e., the sum of squares of residuals) as an objective function, physical key parts of the curve are also considered in the optimization problem. The engineering results of this study indicate that the semiconductor-device-simulation-based MOEA method shows great performance to optimize the parameters, which not only minimize the objective values but also match the curve shape.
Novel Metamorphic HEMTs With Highly Doped InGaAs Source/Drain Regions for High Frequency Applications
(2010-10-01)
Sahoo, Kartika Chandra
;
Kuo, Chien-I
;
Li, Yiming
;
Chang, Edward Yi
;
傳播研究所
In this paper, we report the first result of a strained In(0.52)Ga(0.48) As channel high-electron mobility transistor (HEMT) featuring highly doped In(0.4)Ga(0.6) As source/drain (S/D) regions. A lattice mismatch of 0.9% between In(0.52)Ga(0.48) As and In(0.4)Ga(0.6) As S/D has resulted in a lateral strain in the In(0.52)Ga(0.48) As channel region, where the series resistance is reduced with highly doped S/D regions. An experimentally validated device simulation is advanced for the proposed HEMT, and the results of this paper have shown that there are 60% drive-current and 100% transconductance improvements, compared with the conventional structure. A remarkable 150-GHz increase in the cutoff frequency has been seen for the proposed structure over the conventional one as well for the shown devices.
Numerical simulation and comparison of electrical characteristics between uniaxial strained bulk and SOI FinFETs
(2006-12-01)
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, electrical characteristics of 25 nm strained fin-typed field effect transistors (FinFETs) with oxide-nitride-stacked-capping layer are numerically studied. The FinFETs are fabricated on two different wafers, one is bulk silicon and the other is silicon-on-insulator (SOI) substrate. A three-dimensional device simulation is performed by solving a set of density-gradient-hydrodynamic equations to study device performance including, such as the drain current characteristics (the I-D-V-G and I-D-V-D curves), the drain-induced barrier height lowering, and the subthreshold swing. Comparison between the strained bulk and SOI FinFETs shows that the strained bulk FinFET is promising for emerging multiple-gate nanodevice era according to the manufacturability point of view.
A simulation-based evolutionary technique for inverse doping profile problem of sub-65 nm CMOS devices
(2006-12-01)
Li, Yiming
;
Chen, Cheng-Kai
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we utilize an evolutionary technique for inverse doping profile problems of the 65 nm complementary metal oxide semiconductor (CMOS) devices. The approach mainly bases upon the process simulation, device simulation, evolutionary strategy, and empirical knowledge. For a set of given measured I-V curves of the 65 nm CMOS, a developed prototype performs the optimization task to automatically calibrate and inversely search out, for example the doping recipe and device physical model parameters. The simulation-optimization-coupled methodology is complicated theoretically, but our preliminary results imply that it may benefit the development of fabrication technology and can be used for the performance diagnosis, in particular, for sub-65 nm devices.
Mobility model extraction for surface roughness of SiGe along (110) and (100) Orientations in HKMG bulk FinFET devices
(2013-09-01)
Chen, Chien-Hung
;
Li, Yiming
;
Chen, Chieh-Yang
;
Chen, Yu-Yu
;
Hsu, Sheng-Chia
In this work, the FinFET HKMG MOS devices are fabricated on silicon wafer with p-substrate. The interface roughness between the SiGe and SiO2 is experimentally extracted and calculated as a function of root mean square by analysis of high resolution transmission electron microscopy. The surface-roughness dependent mobility model is then incorporated into device simulation to study the mobility of SiGe along (110) and (100) orientations of the devices. We further analyze four devices with different surface roughness along (100) and (100) orientations to demonstrate the influence of surface roughness on the total effective mobility. (C) 2013 Elsevier B.V. All rights reserved.

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