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Discrete-dopant-fluctuated threshold voltage roll-off in sub-16 nm bulk fin-type field effect transistors
(2008-04-01)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
The effect of the number and position of discrete dopants on device characteristics is crucial in determining the behavior of nanoscale semiconductor devices. We explore the fluctuations of threshold voltage (V(th)) roll-off in nanoscale bulk fin-type field effect transistors (FinFETs) by a three-dimensional (3D) statistically full-scale "atomistic" device simulation technique. The explored devices are of three different dimensions: 16, 22, and 30 nm(3). Discrete dopants are statistically positioned into the 3D channel region to explore associated carrier transport characteristics, concurrently capturing "dopant concentration variation" and "dopant position fluctuation". For the device with a gate length of 16 nm, the V(th) fluctuation of FinFETs is only half that of planar metal-oxide-semiconductor (MOS) FET. Compared with planar MOSFETs, the bulk FinFETs can significantly suppress the fluctuation of V(th) roll-off. The standard deviation of V(th) is proportional to (WL)(-0.25), which is better than the (WL)(-0.5) of planar devices. The superior immunity against fluctuation and the stable fluctuation of V(th) roll-off indicate the bulk FinFET to be a promising device for the sub-16 nm technology era.
Statistical Simulation of Metal-Gate Work-function Fluctuation in High-kappa/Metal-Gate Devices
(2010)
Yu, Chia-Hui
;
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Su, Zhong-Cheng
;
Li, Yiming
In this work, we statistically examine the emerging high-kappa / metal gate work-function fluctuation (WKF) induced threshold voltage (V(th)) fluctuations in 16-nm-gate MOSFET devices. Our Monte-Carlo model extensively evaluates the impact of WKF for different technology node, metal grain size, and gate material. This model provides us to identify suitable materials and fabrication processes that can significantly reduce the impact of Vth fluctuation owing to WKF. First, four kinds of gate material are examined and TiN possesses the smallest Vth fluctuation. For fabrication process, a fast deposition of metal at lower temperature prevents the metal grain not to grow to large size result in a smaller variation. In addition, an idea of modeling multilayer metal gate WKF is also presented and discussed, in which the first layer plays the most important role, compared with other layers, for the fluctuation suppression.
Statistical Analysis of Metal Gate Workfunction Variability, Process Variation, and Random Dopant Fluctuation in Nano-CMOS Circuits
(2009)
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
Han, Ming-Hung
;
Lee, Kuo-Fu
;
Cheng, Hui-Wen
This work for the first time estimates the influences of the intrinsic parameter fluctuations consisting of metal gate workfunction fluctuation (WKF), process variation effect (PVE) and random dopant fluctuation (RDF) on 16-nm-gate planar metal-oxide-semiconductor field effect transistors (MOSFETs) and circuits. The WKF and RDF dominate the threshold voltage fluctuation; however, the WKF brings less impact on the gate capacitance due to the screening effect of the inversion layer. The fluctuation of timing characteristics depends on the threshold voltage fluctuation, and therefore is proportional to the trend of threshold voltage fluctuation. For an amplifier circuit, the high-frequency characteristics, the circuit gain, the 3dB bandwidth, the unity-gain bandwidth power, and the power-added efficiency, are explored consequently. Similar to the trend of the cutoff frequency, the PVE and RDF dominate both the device and circuits characteristic fluctuations due to the significant gate capacitance fluctuations and the WKF is less important at this simulation scenario. The extensive study assesses the fluctuations on circuit performance and reliability, which can in turn be used to optimize nanoscale MOSFET and circuits.
Parameterized Display Performances Behavioral Modeling and Optimization for TFT-LCD Panel
(2009)
Huang, Hsuan-Ming
;
Li, Yiming
;
電信工程研究所
;
Institute of Communications Engineering
In this paper, we implement a systematical method for thin film transistor liquid-crystal display (TFT-LCD) design optimization and sensitivity analysis. Based upon a three-dimensional (3D) field solver, Simulation Program with Integrated Circuit Emphasis (SPICE), and a Design of Experiments, we construct a second-order response surface model (RSM) for the performances of an interested TFT-LCD panel. The constructed RSMs are reduced using a step-wise regression. The adequacy and accuracy using the normal residual plots and their residual of squares are verified. According to the constructed models, we then analyze the sensitivity of the performances by considering the design parameters as changing factors (i.e., the size variation, position shift and driving setting) under an assumption of Gaussian distribution. We also could apply the models to optimize the designed circuit. The designing parameters of these models are selected and optimized to fit the designing target of the examined circuit by the genetic algorithm in our unified optimization framework. This computational statistics method can predict the TFT-LCD performances and show the engineering practicability in display panel industry.
Effect of Process Variation on 15-nm-Gate Stacked Multichannel Surrounding-Gate Field Effect Transistor
(2009)
Han, Ming-Hung
;
Cheng, Hui-Wen
;
Hwang, Chih-Hong
;
Li, Yiming
;
傳播研究所
Stacked multichannel transistor architectures were proposed recently which possess very attractive electrical characteristics on low leakage current and high driving current per layout area. However, due to complex manufacturing process, the process variation effect is inevitable and whose impact is unknown. Therefore, this study investigates the impact of process variation on 15-nm-gate stacked multichannel transistors consisting of the gate length deviation, channel position variation, quadruple-shaped channel structure and elliptic gate oxide. Our preliminary result shows that the stacked multichannel devices have good immunity to the gate length deviation and channel spacing variations; however, they are sensitive to the gate coverage ratio and gate oxide thickness variations. This study provides an insight into the device characteristic variations, which may benefit the development of nanoscale stacked multichannel transistors and circuits.
Comparison of random-dopant-induced threshold voltage fluctuation in nanoscale single-, double-, and surrounding-gate field-effect transistors
(2006-09-01)
Li, Yiming
;
Yu, Shao-Ming
;
資訊工程學系
;
電信工程研究所
;
Department of Computer Science
In this study, we explore random-dopant-induced threshold voltage fluctuation by solving a quantum correction model. Fluctuation of the threshold voltage for three nanoscale transistors, single-, double-, and surrounding-gate (SG, DG, and AG) metal-oxide-semiconductor field-effect transistors (MOSFETs) are computationally compared. To calculate the variance of the threshold voltages of the SG, DG, and AG MOSFETs, a quantum correction model under equilibrium conditions is expanded and numerically solved using perturbation and monotone iterative methods. Fluctuation of the threshold voltage resulting from the random dopant, gate oxide thickness, channel film thickness, gate channel length, and device width are calculated for the three devices. Quantum mechanical and classical results give similar predictions for fluctuation of the threshold voltage with respect to different parameters including the dimensions of the device and the channel doping. Fluctuation increases when the channel doping concentration, channel film thickness, and gate oxide thickness increase, On the other hand, it decreases when the channel length and device width increase. Calculation results of the quantum correction model are quantitatively higher than those of classical estimation in accordance with different quantum confinement effects in nanoscale SG, DG, and AG MOSFETs. It is found that the AG MOSFET has the smallest threshold voltage fluctuation among the three device structures due to its good channel controllability. In contrast to the conventional quantum Monte Carlo approach and the small-signal analysis of the Schrodinger-Poisson equations, this computationally cost-effective quantum correction approach shows acceptable accuracy and is ready for industrial technology computer-aided design application.
Effect of fin angle on electrical characteristics of nanoscale round-top-gate bulk FinFETs
(2007-12-01)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
In this brief, electrical characteristics of 25-nm round-top-gate fin-typed field-effect transistors (FinFETs) on silicon wafers are numerically explored. With an ideal fin angle (i.e., theta = 90 degrees), the FinFETs with doped and undoped (for this case, the device has a metal gate) channels that was fabricated on silicon and silicon-on-insulator wafers are simulated and compared. With a 3-D quantum-correction-transport simulation, characteristic comparison shows that bulk FinFETs with the undoped channel possess promising electrical characteristics. By considering different short-channel effects, dependence of the device performance on the nonideal fin angle and fin height is further investigated. Optimal structure configuration for the round-top-gate bulk FinFETs is thus drawn to show the strategy of fabrication in sub-25-mn MOSFET devices.
High-Frequency Characteristic Fluctuations of Nano-MOSFET Circuit Induced by Random Dopants
(2008-12-01)
Li, Yiming
;
Hwang, Chih-Hong
;
電信工程研究所
;
Institute of Communications Engineering
As the dimension of semiconductor device shrunk into nanometer scale (nanoscale), characteristic fluctuation is more pronounced, and become crucial for circuit design. In this paper, discrete-dopant-induced characteristic fluctuation of 16-nm-gate metal-oxide-semiconductor field effect transistors (MOSFET) circuit under high-frequency regime is quantitatively studied. The circuit gain, the 3 dB bandwidth and the unity-gain bandwidth of the tested nanoscale transistor circuit are calculated concurrently capturing the discrete-dopant-number- and discrete-dopant-position-induced fluctuations in the large-scale statistically sound "atomistic" device/circuit coupled simulation. For the 16-nm-gate MOSFET circuit, the number of discrete dopants, varying from zero to 14, may result in 5.7% variation of the circuit gain, 14.1% variation of the 3 dB bandwidth, and 10.4% variation of the unity-gain bandwidth. To suppress the high-frequency characteristic fluctuations, an improved doping distribution along the longitudinal diffusion direction from the MOSFET's surface to substrate is further performed to examine the associated fluctuation. The improved vertical doping profile with less dopants locating near surface of channel effectively reduces the fluctuations of the circuit gain, the 3 dB bandwidth and the unity-gain bandwidth dramatically. Compared with the original doping profile, the reduction is 32.3%, 19.4% and 51.8%, respectively. This study provides an insight into random-dopant-induced intrinsic high-frequency characteristic fluctuations and verifies the potential fluctuation suppression technique on high-frequency characteristic fluctuations of nanoscale transistor circuit.
Discrete-Dopant-Induced Timing Fluctuation and Suppression in Nanoscale CMOS Circuit
(2009-05-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
電信工程研究所
;
Institute of Communications Engineering
As the dimensions of semiconductor devices continue to be reduced, device fluctuations have become critical to determining the accuracy of timing in circuits and systems. This brief studies the discrete-dopant-induced timing characteristic fluctuations in 16-nm-gate complementary metal-oxide-semiconductor (CMOS) circuits using a 3-D "atomistic" coupled device-circuit simulation. The accuracy of the simulation has been confirmed by using the experimentally calibrated transistor physical model. For a 1.6-nm-gate CMOS inverter, 3.5%, 2.4%, 18.3%, and 13.2% normalized fluctuations in the rise time, fall time, high-to-low delay time, and low-to-high delay time, respectively, are found. Random dopants may cause significant timing fluctuations in the studied circuits. Suppression approaches that are based on the circuit and device design viewpoints are implemented to examine the associated characteristic fluctuations. The use of shunted transistors in the circuit provides similar suppression to the use of a device with doubled width. However, both approaches increase the chip area. To eliminate the need to increase the chip area, channel engineering approaches (vertical and lateral) are proposed, and their effectiveness in reducing the timing fluctuation is demonstrated.
Random-Dopant-Induced Variability in Nano-CMOS Devices and Digital Circuits
(2009-08-01)
Li, Yiming
;
Hwang, Chih-Hong
;
Li, Tien-Yeh
;
電信工程研究所
;
Institute of Communications Engineering
The impact of the number and position of discrete dopants on device characteristics is crucial in determining the transient behavior of nanoscale circuits. An experimentally validated coupled device-circuit simulation was conducted to investigate the discrete-dopant-induced timing-characteristic fluctuations in 16-nm-gate CMOS circuits. The random-doping effect may induce 18.9% gate-capacitance fluctuation, affecting the intrinsic device gate delay and circuit timing. For a 16-nm-gate CMOS inverter, 0.036-, 0.021-, 0.105-, and 0.108-ps fluctuations in rise time, fall time, low-to-high delay time, and high-to-low delay time are found. The timing fluctuations of NAND and NOR circuits are increased, as the number of transistors increased. Because of the same number of transistors in circuits, the timing fluctuation of NAND and NOR are expected to be similar. However, due to the different function and device operation status of circuit, the timing fluctuation is quite different. The function-and circuit-topology-dependent characteristic fluctuations caused by random nature of discrete dopants are found. This paper provides an insight into random-dopant-induced intrinsic timing fluctuations, which can, in turn, be used to optimize nanoscale CMOS field-effect-transistor circuits.

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