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Now showing 1 - 10 of 66
  • Item type:Item,
    Mobility enhancements in AlGaN/GaN/SiC with stair-step and graded heterostructures
    (1997-05-12)
    Lin, CF
    ;
    Cheng, HC
    ;
    Huang, JA
    ;
    Feng, MS
    ;
    Guo, JD
    In this letter, we report the observation of the enhanced electron mobility in three different Al0.08Ga0.92N/GaN heterostructures. These structures were deposited on (0001) 6H-SiC substrates by using the low-pressure metalorganic chemical vapor deposition method. The structure was composed of 500 Angstrom AlGaN compositional stair-step layer deposited onto 1.3 mu m GaN epitaxial layer. There is a 100 Angstrom GaN Cap layer on top of the AlGaN layer to prevent the oxidation of the AlGaN layer. By using the van der Pauw method of Hall measurement, the sheet carrier density and mobility for Al0.08Ga0.92N/GaN heterostructure are 6.6x10(12) cm(-2) and 5413 cm(2)/Vs at 77 K, respectively. This high value of mobility is, to the best of our knowledge, the first observed two-dimensional electron gas (2DEG) at the AlGaN/GaN stair-step type of heterostructure. Other interface structures such as graded composition and bulk composition structures were also prepared and 2DEG properties were observed. (C) 1997 American Institute of Physics.
  • Item type:Item,
    Growth and characterizations of GaN on SiC substrates with buffer layers
    (1997-09-01)
    Lin, CF
    ;
    Cheng, HC
    ;
    Chi, GC
    ;
    Feng, MS
    ;
    Guo, JD
    High quality GaN epitaxial layers were grown on 6H-SiC substrates by using low-pressure metalorganic chemical vapor deposition method, Samples employing a three-period GaN/Al0.08Ga0.92N (100 Angstrom/100 Angstrom) as a buffer layer produce a good quality GaN epitaxial layer, with mobility and carrier concentration of 612 cm(2)/V.s and 1.3x10(17) cm(-3) (at 300 K), respectively, The enhanced electron mobility in the Al0.08Ga0.92N/GaN heterostructures is also observed, By using the van der Pauw method of Hall measurement, the sheet carrier density and mobility at 4.2 K for the Al0.08Ga0.92N/GaN heterostructure are 5.8x10(12) cm(-2) and 5300 cm(2)/V.s, respectively. Strong SdH (Shubnikov-de Haas) oscillations were observed to confirm the two-dimensional electron gas (2DEG) phenomenon at the AlGaN/GaN top heterointerface. In addition, an extra SdH oscillation also resulted from the high-duality 2DEG channel of the GaN/AlGaN bottom heterointerface. (C) 1997 American Institute of Physics.
  • Item type:Item,
    Process optimization of plasma-enhanced chemical vapor deposited passivation thin films for improving nonvolatile memory IC performance
    (1998-12-01)
    Lin, CF
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    Characteristics of plasma-enhanced chemical vapor deposited (PECVD) SiO2/SiNx passivation layers are modified to improve and optimize electrical performances such as program/erase cycle and hot carrier reliability of floating-gate nonvolatile memory devices. SiH4/N2O gas mixtures are utilized as precursors for oxide CVD process. Higher SiH4/N2O flow rate ratios render the resulting oxide films more silicon-rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics also correspond to increased program/erase cycles and lower % hot-carrier linear drain current (I-dlin) degradation An increase in RI from 1.520 to 1.675 translates to a rise in program/erase cycles from 17.3 K to 32 K and a fall in I-dlin from 8.2% to 4.9%. Further improvement in device performance is fulfilled by modifying the stoichiometry of the overlying nitride passivation layer. Water diffusion from oxide and hydrogen release from nitride are both responsible for hot carrier drain current degradation and loss in program/erase cycles. The utilization of a high-RI oxide in conjunction with a low hydrogen content nitride would give rise to the optimal device reliability.
  • Item type:Item,
    The effect of lead impurity on the DC-etching behaviour of aluminum foil for electrolytic capacitor usage
    (1996-06-01)
    Lin, W
    ;
    Tu, GC
    ;
    Lin, CF
    ;
    Peng, YM
    ;
    材料科學與工程學系
    The effects of lead impurity on the etched morphology of high purity aluminum foils for electrolytic capacitor applications were investigated in this work. The lead impurity was either present in as-received aluminum foils or deposited purposely on the foil surface through an immersion-reduction reaction. The amount and distribution of deposited lead varies with the lead content in as-received foil. The as-received foil with higher lead content gave a higher concentration and a more uniform distribution of deposited lead. Uniformly distributed vertical tunnel etchings were obtained when high lead foil, formed by immersion as-received high lead foil in Pb(NO3)(2) solution, was subject to DC-etching. For the as-received lower lead foils, the deposited lead was concentrated in rolling lines which resulted in surface etching along rolling lines. Both the surfacial and cross-sectional etching morphologies are presented in this study, together with the etching mechanism discussed. Copyright (C) 1996 Elsevier Science Ltd.
  • Item type:Item,
    A modified multi-chemical spray cleaning process for post shallow trench isolation chemical mechanical polishing cleaning application
    (1998-11-02)
    Wang, YL
    ;
    Wang, TC
    ;
    Wu, J
    ;
    Tseng, WT
    ;
    Lin, CF
    Chemical mechanical planarization (CMP) has become widely accepted for the formation of device interconnect structures. Shallow trench isolation technology (STI) utilizes CMP and has been applied to deep-sub-micron processes. Poly Si, CVD Si or SiO2 can be grown or deposited in the trench and planarized by a CMP process. However, the typical wafer surface is contaminated with slurry particles and metallic impurities after the CMP process. The silica particles may damage the VLSI patterns and the metallic impurities can induce many crystal defects in Si wafers during the following furnace processing. Therefore, the post CMP clean is a very important step for the STI process. However, the wafer for poly-Si surface is hydrophobic, SiO2 surface is hydrophilic and Si film is very easy to charge up. Thus, the defect can be difficult to remove by a conventional cleaning technique. In this study: we propose the use of a modified multi-chemicals spray cleaning process for post STI CMP cleaning. We used a modified and heated ammonia/peroxide mix (APM) clean with an ammonia pre-soak and an HF step to etch a thin layer for the removal of trapped metallic ions which can be followed by a hydrochloric/peroxide mix (HPM) clean process to assist in the removal of metallic ions. (C) 1998 Elsevier Science S.A. All rights reserved.
  • Item type:Item,
    Process optimization of plasma-enhanced chemical vapor deposited passivation thin films for improving nonvolatile memory IC performance
    (1998-12-01)
    Lin, CF
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    Characteristics of plasma-enhanced chemical vapor deposited (PECVD) SiO2/SiNx passivation layers are modified to improve and optimize electrical performances such as program/erase cycle and hot carrier reliability of floating-gate nonvolatile memory devices. SiH4/N2O gas mixtures are utilized as precursors for oxide CVD process. Higher SiH4/N2O flow rate ratios render the resulting oxide films more silicon-rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics also correspond to increased program/erase cycles and lower % hot-carrier linear drain current (I-dlin) degradation An increase in RI from 1.520 to 1.675 translates to a rise in program/erase cycles from 17.3 K to 32 K and a fall in I-dlin from 8.2% to 4.9%. Further improvement in device performance is fulfilled by modifying the stoichiometry of the overlying nitride passivation layer. Water diffusion from oxide and hydrogen release from nitride are both responsible for hot carrier drain current degradation and loss in program/erase cycles. The utilization of a high-RI oxide in conjunction with a low hydrogen content nitride would give rise to the optimal device reliability.
  • Item type:Item,
    Blind adaptive energy estimation for decorrelating decision-feedback CDMA multiuser detection using learning-type stochastic approximations
    (1999-03-01)
    Chang, PR
    ;
    Lee, CC
    ;
    Lin, CF
    ;
    電信工程研究所
    ;
    Institute of Communications Engineering
    This paper investigates the application of linear reinforcement learning stochastic approximation to the blind adaptive energy estimation for a decorrelating decision-feedback (DDF) multiuser detector over synchronous code-division multiple-access (CDMA) radio channels in the presence of multiple-access interference (MAI) and additive Gaussian noise. The decision feedback incorporated into the structure of a linear decorrelating detector is able to significantly improve the weaker users' performance by canceling the MAI from the stronger users. However, the DDF receiver requires the knowledge of the received energies, In this paper, a new novel blind estimation mechanism is proposed to estimate all the users' energies using a stochastic approximation algorithm without training data. In order to increase the convergence speed of the energy estimation, a linear reinforcement learning technique is conducted to accelerate the stochastic approximation algorithms. Results show that our blind adaptation mechanism is able to accurately estimate an the users' energies even if the users of the DDF detector are not ranked properly. After performing the blind energy estimation and then reordering the users in a nonincreasing order, numerical simulations show that the DDP detector for the weakest user performs closely to the maximum likelihood detector, whose complexity grows exponentially with the number of users.
  • Item type:Item,
    Optimization of multilayer thin film passivation processes for improving cache memory device performance
    (1999-04-01)
    Lin, CF
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    A multilayer thin film passivation structure based on alternating plasma-enhanced chemical vapor deposited (PECVD) SiOx-SiNx layers are prepared and characterized, in order to improve and optimize the electrical performance and hot carrier reliability of polyload resistors in 4-transistor (4-T) cache static random access memory devices. SiH4-N2O gas mixtures are utilized as precursors for oxide CVD process. Adopting a higher SiH4/N2O flow rate ratio during deposition renders the resulting oxide films more silicon rich, as manifested by their higher refractive index (RI) and wet etch rates. These modifications in film characteristics are also accompanied by enhanced resistance of polyload resistor and lower percentage hot-carrier linear drain current (I-dlin) degradation. An increase in RI from 1.46 to 1.67 translates to a rise in resistance of polyload resistor from 98 to 225 G Omega and a fall in I-dlin from 5.8 to 4.5%. Further improvement in device performance can be realized by modifying the stoichiometry of the overlying nitride passivation layer. This is achieved by increasing bias power while reducing the SiH4/NH3 gas flow rate ratio during the PECVD nitride deposition process. The nitride thus thus deposited contain lower Si-H bond density, and exhibit lower buffered oxide etch rates and compressive stress. Passivation structures based on the combination of a high RI oxide and a low Si-H content nitride layers yield the most promising device performance and reliability. Defect species in the oxide passivation layer are identified and their charge trapping mechanisms clarified. Impact of moisture and hydrogen from the passivation on polygate and load resistor are both held responsible for device degradation. Interfacial defect reactions involving both hydrogen and moisture are proposed to account for the carrier trapping mechanisms responsible for device failure. (C) 1999 The Electrochemical Society. S0013-4651(98)02-078-3. All rights reserved.
  • Item type:Item,
    Process optimization and integration for silicon oxide intermetal dielectric planarized by chemical mechanical polish
    (1999-05-01)
    Lin, CF
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    材料科學與工程學系
    ;
    Department of Materials Science and Engineering
    The chemical mechanical planarization (CMP) characteristics of silicon oxide films are studied systematically for the optimization of planarization for intermetal dielectric (IMD) processes. By way of orthogonal array experimental design, the influences of physical parameters during CMP upon the polishing behaviors of silicon oxide dielectric materials are investigated. Polishing results with a removal rate greater than 200 nm/min and a within-wafer nonuniformity less than 4% can be achieved and an optimized polish process is derived from parametric experiments, which are based on the summarized trends from orthogonal array experimental results. The optimized polish process is applied to planarize patterned IMD wafers with different metal line pitch and IMD thickness. Incorporating the IMD geometric factors and CMP polishing performance, a rule including the integral nonuniformity, thickness of dielectric, efficiency of planarization, geometry of device, removal rate, and its variation for CMP time estimation (INTEGRATE) is proposed to approximate the required IMD thickness and CMP polish time for ImD process integration. High efficiency of the planarization process and excellent planarity are both achieved based on the rule of INTEGRATE. (C) 1999 The Electrochemical Society. S0013-4651(98)09-059-4. All rights reserved.
  • Item type:Item,
    A ULSI shallow trench isolation process through the integration of multilayered dielectric process and chemical-mechanical planarization
    (1999-06-22)
    Lin, CF
    ;
    Tseng, WT
    ;
    Feng, MS
    ;
    Wang, YL
    ;
    材料科學與工程學系
    A multilayer thin film structure (SiO2/SiNx/SiO2) with a one-step chemical-mechanical polish (CMP) process is developed for shallow trench filling and planarization for ULSI devices in the quarter micron regime. By fine-tuning the plasma-enhanced chemical vapor deposition (PECVD) conditions we successfully modified the stoichiometry and other characteristics of the as-deposited SiNx and oxide films. As these film characteristics are changed, the CMP removal rate selectivity between sacrificial oxide and nitride stopper layer can also be adjusted. Correspondingly, the CMP process latitude for shallow trench isolation in 0.25 mu m memory devices can be broadened by sequentially depositing multilayered oxide and nitride films with adjustable characteristics and CMP removal rates. Dishing-free wide trench areas with excellent planarity can be achieved through the integration of the proposed multilayered PECVD oxide/nitride scheme and the one-step CMP process. (C) 1999 Elsevier Science S.A. All rights reserved.