學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Search Results

Now showing 1 - 10 of 12

Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process
(2016-11)
Lin, Chun-Yu
;
Wu, Yi-Han
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional process step. The proposed device uses two metal gates to separate the anode and cathode of the SCR to reduce the leakage current. These two gates are well controlled to trigger the SCR device. The test devices have been implemented and verified in a 28-nm high-k metal gate CMOS process. Experimental results show that the proposed SCR exhibits a low trigger voltage (<3 V), low leakage current (<5 nA), low parasitic capacitance (<40 fF), and sufficient ESD robustness (>1 kV in human-body-model tests). Based on its good performances during ESD stress and normal circuit operating conditions, the proposed SCR device is very suitable for ESD protection in advanced CMOS processes.
On-Chip ESD Protection Designs in RF Integrated Circuits for Radio and Wireless Applications
(2013)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
CMOS technology has been used to implement the radio and wireless integrated circuits. However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness. Therefore, on-chip ESD protection designs must be added at all input/output pads in CMOS chip. To minimize the impacts from ESD protection design on circuit performances, ESD protection at input/output pads must be carefully designed. A review on ESD protection designs with low parasitic capacitance for radio and wireless applications is presented in this paper. The comparisons among these ESD protection designs are also discussed.
SCR Device for On-Chip ESD Protection in RF Power Amplifier
(2013)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To protect a radio-frequency (RF) power amplifier from electrostatic discharge (ESD) damages, a lowcapacitance, high-robust, and good-latch up-immune ESD protection device was proposed in this work. T he proposed design has been realized in a compact structure in a 65-nm CMOS process. Experimental results of the test devices have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
Investigation on SCR-based ESD protection device for biomedical integrated circuits in a 0.18-mu m CMOS process
(2015-11-01)
Lin, Chun-Yu
;
Chiu, Yan-Lian
;
生醫電子轉譯研究中心
;
Biomedical Electronics Translational Research Center
In these decades, integrated circuits for biomedical electronics applications have been designed and implemented in CMOS technologies. In order to be safely used by human, all microelectronic products must meet the reliability specifications. Therefore, electrostatic discharge (ESD) must be taken into consideration. To protect the biomedical integrated circuits in CMOS technologies from ESD damage, a dual-directional silicon-controlled rectifier (DDSCR) device was presented in this work. Experimental results show that the DDSCR has the advantages of high ESD robustness, low leakage, large swing tolerance, and good latchup immunity. The DDSCR was suitable for ESD protection in biomedical integrated circuits. (C) 2015 Elsevier Ltd. All rights reserved.
Impact of Inner Pickup on ESD Robustness of Multifinger MOSFET in 28-nm High-k/Metal Gate CMOS Process
(2015-12-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The impact of pickup structure on electrostatic discharge (ESD) robustness of multifinger MOSFET in 28-nm high-k/metal gate CMOS process was investigated in this paper. Verified in silicon, the multifinger MOSFET without the pickup structure inserted into its source region can sustain the higher ESD level and more compact layout area.
Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process
(2015-04-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.
Overview on ESD Protection Designs of Low-Parasitic Capacitance for RF ICs in CMOS Technologies
(2011-06-01)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
Hsiao, Yuan-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
CMOS technology has been widely used to implement radio-frequency integrated circuits (RF ICs). However, the thinner gate oxide in nanoscale CMOS technology seriously degrades the electrostatic discharge (ESD) robustness of RF ICs. Therefore, on-chip ESD protection designs must be added at all input/output pads in RF circuits against ESD damages. To minimize the impacts from ESD protection circuit on RF performances, ESD protection circuit at input/output pads must be carefully designed. An overview on ESD protection designs with low parasitic capacitance for RF circuits in CMOS technology is presented in this paper. The comparisons among these ESD protection designs are also discussed. With the reduced parasitic capacitance, ESD protection circuit can be easily combined or co-designed with RF circuits. As the operating frequencies of RF circuits increase, on-chip ESD protection designs for RF applications will continuously be an important design task.
Compact and Low-Loss ESD Protection Design for V-Band RF Applications in a 65-nm CMOS Technology
(2012)
Chu, Li-Wei
;
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
Nanoscale CMOS technologies have been widely used to implement radio-frequency (RF) integrated circuits. However, the thinner gate oxide and silicided drain/source in nanoscale CMOS technologies seriously degrade the electrostatic discharge (ESD) robustness of RF circuits. Against ESD damage, on-chip ESD protection design must be included in RF circuits. As the RF circuits operating in the higher frequency band, the parasitic effect from ESD protection devices and/or circuits must be strictly limited. To provide the effective ESD protection for a 60-GHz low-noise amplifier (LNA) with less RF performance degradation, a new ESD protection design was studied in a 65-nm CMOS process. Such ESD-protected LNA with simulation/measurement results has been successfully verified in silicon chip to to achieve the 2-kV HBM ESD robustness with the lower power loss in a smaller layout area.
Large-Swing-Tolerant ESD Protection Circuit for Gigahertz Power Amplifier in a 65-nm CMOS Process
(2013-02-01)
Lin, Chun-Yu
;
Tsai, Shiang-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
The signal swing at output pad of some radio-frequency (RF) power amplifiers (PAs) may be higher than the supply voltage. To protect the gigahertz large-swing power amplifier from electrostatic discharge (ESD) damage in nanoscale CMOS process, a large-swing-tolerant ESD protection circuit is presented in this paper. The proposed ESD protection circuit had been designed, fabricated, and characterized in a 65-nm CMOS process, where it can achieve low parasitic capacitance, large swing tolerance, high ESD robustness, and good latchup immunity. The proposed ESD protection circuit had been further applied to a 2.4-GHz PA to provide 3-kV human-body-model (HBM) ESD robustness without degrading the RF performances.
ESD Protection Structure with Inductor-Triggered SCR for RF Applications in 65-nm CMOS Process
(2012)
Lin, Chun-Yu
;
Chu, Li-Wei
;
Ker, Ming-Dou
;
Song, Ming-Hsiang
;
Jou, Chewn-Pu
To protect radio-frequency (RF) integrated circuits from electrostatic discharge (ESD) damages, silicon-controlled rectifier (SCR) devices have been used as main on-chip ESD protection devices due to their high ESD robustness and low parasitic capacitance in nanoscale CMOS technologies. In this work, the SCR device assisted with an inductor to resonate at the selected frequency band for RF performance fine tune was proposed. Besides, the inductor can be also designed to improve the turn-on efficiency of the SCR device for ESD protection. Verified in a 65-nm CMOS process, the ESD protection design with the inductor-triggered SCR for 60-GHz RF applications can achieve good RF performances and high ESD robustness.

學術出版;;Publications

Browse

Filters

Settings

Sort By

Results per page

🏛️國立陽明交通大學機構典藏

Search Results