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Design of Fin-Diode-Triggered Rotated Silicon-Controlled Rectifier for High-Speed Digital Application in 16-nm FinFET Process
(2020-07-01)
Chang, Rong-Kun
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The FinFET architecture has widely been used in the digital circuit application, due to the good short channel effect control and driving current boost. However, the worse thermal dispassion and smaller effective silicon volume would cause the significant impacts during the circuits under electrostatic discharge (ESD) event. Thus, the ESD protection device should be installed into the high-speed digital circuit to enhance the ESD robustness. To avoid the effect of circuit performance, the parasitic capacitance of ESD device must be as low as possible. In this article, two types of Fin-diode-triggered rotated silicon-controlled rectifier (SCR) with dual ESD current path have been proposed and verified in a 16-nm FinFET CMOS process. The proposed devices have better current-handling capability, sufficiently low parasitic, compact layout area, and low leakage current.
On-Chip HBM and HMM ESD Protection Design for RF Applications in 40-nm CMOS Process
(2018-12-01)
Chen, Jie-Ting
;
Lin, Chun-Yu
;
Chang, Rong-Kun
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
On-chip electrostatic discharge (ESD) protection device with large dimension can sustain high-ESD current, but the parasitic capacitance of the ESD protection device will increase the difficulty of impedance matching and degrade the bandwidth for broadband radio frequency (RF) applications. The traditional distributed ESD protection circuit can achieve good impedance matching, but it has a worse ESD robustness because of larger resistance caused by the input inductor. In this paper, a new distributed ESD protection structure with the stacked diodes with embedded silicon-controlled rectifier is proposed to attain good ESD robustness without degrading the RF performance. The proposed ESD protection circuit has been successfully verified in a 40-nm, 2.5-V CMOS process to sustain a human-metal model of 5 kV. The proposed ESD protection circuit is suitable to protect the broadband RF circuits in advanced nanoscale CMOS technology.
On-Chip ESD Protection Device for High-Speed I/O Applications in CMOS Technology
(2017-10-01)
Chen, Jie-Ting
;
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The diode operated under forward-biased condition has been widely used as an on-chip electrostatic discharge (ESD) protection device for high-speed circuits to sustain high ESD robustness, but the parasitic capacitance of diode may bring a negative impact to the circuits operating at higher speed. The ESD protection design with low parasitic capacitance has been strongly requested in high-speed I/O applications. The traditional methods to reduce parasitic capacitance were using a stacked diode or a stacked diode with embedded silicon-controlled rectifier (SCR). The stacked diode or the stacked diode with embedded SCR would have larger turn-on resistance to cause a higher clamping voltage. It should be further improved to achieve good ESD protection effectiveness for the high-speed I/O applications. In this paper, a new ESD protection device with reduced parasitic capacitance and smaller turn-on resistance to improve ESD protection effectiveness is proposed. The measurement results from the silicon chip have demonstrated that the proposed ESD device can achieve smaller parasitic capacitance, lower turn-on resistance, and higher ESD robustness, compared with the conventional devices. The proposed ESD protection device is very suitable to protect the high-speed I/O circuits in nanoscale CMOS technology.
Low-Leakage and Low-Trigger-Voltage SCR Device for ESD Protection in 28-nm High-k Metal Gate CMOS Process
(2016-11)
Lin, Chun-Yu
;
Wu, Yi-Han
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To effectively protect integrated circuits from electrostatic discharge (ESD) damage, this letter proposes a silicon-controlled rectifier (SCR) device with low trigger voltage, low leakage current, low parasitic capacitance, and which requires no additional process step. The proposed device uses two metal gates to separate the anode and cathode of the SCR to reduce the leakage current. These two gates are well controlled to trigger the SCR device. The test devices have been implemented and verified in a 28-nm high-k metal gate CMOS process. Experimental results show that the proposed SCR exhibits a low trigger voltage (<3 V), low leakage current (<5 nA), low parasitic capacitance (<40 fF), and sufficient ESD robustness (>1 kV in human-body-model tests). Based on its good performances during ESD stress and normal circuit operating conditions, the proposed SCR device is very suitable for ESD protection in advanced CMOS processes.
SCR Device for On-Chip ESD Protection in RF Power Amplifier
(2013)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
To protect a radio-frequency (RF) power amplifier from electrostatic discharge (ESD) damages, a lowcapacitance, high-robust, and good-latch up-immune ESD protection device was proposed in this work. T he proposed design has been realized in a compact structure in a 65-nm CMOS process. Experimental results of the test devices have been successfully verified, including RF performances, I-V characteristics, and ESD robustness.
Study on the ESD-Induced Gate-Oxide Breakdown and the Protection Solution in 28nm High-K Metal-Gate CMOS Technology
(2015)
Lin, Chun-Yu
;
Ker, Ming-Dou
;
Chang, Pin-Hsin
;
Wang, Wen-Tai
;
電子工程學系及電子研究所
To protect the IC chips against the electrostatic discharge (ESD) damages in 28nm high-k metal-gate (HKMG) CMOS technology, the ESD protection consideration was studied in this work. The ESD design window was found to be within 1V and 5.1V in 28nm HKMG CMOS technology. An ESD protection device of PMOS with embedded silicon-controlled rectifier (SCR) was investigated to be suitable for ESD protection in such narrow ESD design window.
Improving ESD Robustness of Stacked Diodes with Embedded SCR for RF Applications in 65-nm CMOS
(2014)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
Ker, Ming-Dou
;
Chu, Li-Wei
;
Tseng, Jen-Chou
To protect the radio-frequency (RF) integrated circuits from the electrostatic discharge (ESD) damage in nanoscale CMOS process, the ESD protection circuit must be carefully designed. In this work, stacked diodes with embedded silicon-controlled rectifier (SCR) to improve ESD robustness was proposed for RF applications. Experimental results in 65-nm CMOS process show that the proposed design can achieve low parasitic capacitance, low turn-on resistance, and high ESD robustness.
Design of ESD Protection Diodes With Embedded SCR for Differential LNA in a 65-nm CMOS Process
(2014-11-01)
Lin, Chun-Yu
;
Fan, Mei-Lian
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
The pin-to-pin electrostatic discharge (ESD) issue for a differential low-noise amplifier (LNA) was studied in this work. A new design of ESD protection diodes with an embedded silicon-controlled rectifier (SCR) was proposed to protect the gigahertz differential LNA. The proposed ESD protection design was modified from the conventional ESD protection design without adding any extra device. The SCR path was established directly from one differential input pad to the other differential input pad so the pin-to-pin ESD robustness can be improved. This design had been verified in a 65-nm CMOS process. Besides, this design had been further applied to a 24-GHz LNA in the same 65-nm CMOS process. Experimental results had shown that the proposed ESD protection design for the differential LNA can achieve excellent ESD robustness and good RF performances.
Improving ESD Robustness of pMOS Device With Embedded SCR in 28-nm High-k/Metal Gate CMOS Process
(2015-04-01)
Lin, Chun-Yu
;
Chang, Pin-Hsin
;
Chang, Rong-Kun
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A pMOS device with an embedded silicon-controlled rectifier to improve its electrostatic discharge (ESD) robustness has been proposed and implemented in a 28-nm high-k/metal gate CMOS process. An additional p-type ESD implantation layer was added into the pMOS to realize the proposed device. The experimental results show that the proposed device has the advantages of high ESD robustness, low holding voltage, low parasitic capacitance, and good latchup immunity. With better performances, the proposed device was more suitable for ESD protection in a sub-50-nm CMOS process.
Low-capacitance SCR with waffle layout structure for on-chip ESD protection in RF ICs
(2008-05-01)
Ker, Ming-Dou
;
Lin, Chun-Yu
;
電機學院
;
College of Electrical and Computer Engineering
The silicon-controlled rectifier (SCR) has been used as an effective on-chip electrostatic discharge (ESD) protection device in CMOS technology due to the highest ESD robustness in nanoscale integrated circuits (10). In this study, the SCR realized in a waffle layout structure is proposed to improve ESD current distribution efficiency for ESD protection and to reduce the parasitic capacitance. The waffle layout structure of the SCR can achieve smaller parasitic capacitance under the same ESD robustness. With smaller parasitic capacitance, the degradation on RF circuit performance due to ESD protection devices can be reduced. The proposed waffle SCR with low parasitic capacitance is suitable for on-chip ESD protection in RF ICs. Besides, the desired current to trigger on the SCR device with a waffle layout structure and its turn-on time has also been investigated in a silicon chip.

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