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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Lin, HCSubject: search.filters.subject.ashing

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    Enhanced negative-bias-temperature instability of P-channel metal-oxide-semiconductor transistors due to plasma charging damage
    (2002-04-01)
    Lee, DY
    ;
    Lin, HC
    ;
    Wang, MF
    ;
    Tsai, MY
    ;
    Huang, TY
    The effects of plasma charging on the negative-bias-temperature instability (NBTI) of p-channel metal-oxide-semiconductor (PMOS) transistors were explored in this work. It is clearly shown that the threshold voltage shift during bias-temperature stressing (BTS) could be enhanced by plasma charging damage. More importantly, we also found that electron trappings are aggravated by plasma charging, even on new devices with large antenna area ratios prior to BTS. Our charge pumping current measurements confirm that the interface-state density is increased for devices with large antennas, both before and after the BTS. This indicates, without ambiguity, that electron trapping is solely responsible for the observed low (in absolute value) threshold voltage in new devices with large antennas. Finally, it is proposed that the NBTI characterization can be used as a sensitive method for characterizing the antenna effects in devices with ultrathin gate oxide, which is particularly attractive in light of the fact that conventional indicators are becoming inadequate as oxide is scaled down.
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    The role of a resist during O-2 plasma ashing and its impact on the reliability evaluation of ultrathin gate oxides
    (1997-07-01)
    Chien, CH
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    Chang, CY
    ;
    Lin, HC
    ;
    Chang, TF
    ;
    Hsien, SK
    Resists are regarded as protective layers for underlying devices during plasma ashing. In previous studies, resists were deliberately removed by a wet etching process prior to plasma exposure in an effort to achieve significant device degradation. In this paper we report that, contrary to conventional belief, devices with a resist overlayer actually suffer from more severe degradation than those without a resist covering. This resist-enhanced degradation effect, although not observed for devices with a thick gate oxide of 8 nm, becomes significant as the oxide thickness is scaled down below 6 nm. The most severe device degradation is found to be located at the center of the wafer and is found to increase with increasing antenna area ratio. Damage is also found to occur not during the overashing period, but primarily during the initial ashing stage when the resist is still on the electrodes. Using a combination of a simple equivalent capacitor circuit model and the self-adjustment behavior of potential between the wafer surface and substrate, good correlation with the experimental results is obtained.