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Author: search.filters.author.Lin, HCSubject: search.filters.subject.thin-film transistor

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    A novel thin-film transistor with self-aligned field induced drain
    (2001-01-01)
    Lin, HC
    ;
    Yu, CM
    ;
    Lin, CY
    ;
    Yeh, KL
    ;
    Huang, TY
    In this letter, a novel thin-film transistor with a self-aligned field-induced-drain (SAFID) structure is reported for the first time. The new SAFID TFT features a self-aligned sidewall spacer located on top of the drain offset region to set its effective length, and a bottom gate (or field plate) situated under the drain offset region to electrically induce the field-induced-drain (FID). So, unlike the conventional off-set-gated TFTs with their effective FID length set by two separate photolithographic masking layers, the new SAFID is totally immune to photomasking misalignment errors, while enjoying the low off-state leakage as well as high turn-on characteristics inherent in the FID structure. Polycrystalline silicon TFTs with the new SAFID structure have been successfully fabricated with significant improvement in the on/off current ratio.
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    Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain extension
    (2001-04-01)
    Lin, HC
    ;
    Yeh, KL
    ;
    Huang, RG
    ;
    Lin, CY
    ;
    Huang, TY
    A novel Schottky barrier thin-film transistor (SBTFT) with silicided source/drain and field-induced drain (FID) extension is proposed and demonstrated. In the new device configuration, a metal field-plate (or sub-gate) lying on the passivation oxide is employed to induce a sheet of carriers in a channel offset region located between the silicided drain and the active channel region underneath the main-gate. The new device thus allows ambipolar device operation by simply switching the polarity of the bias applied to the field plate. In contrast to the conventional SBTFT that suffers from high GIDL (gate-induced drain leakage)-like off-state leakage current, the new SBTFT with FID is essentially free from the GIDL-like leakage current. In addition, unlike the conventional SBTFT that suffers from the low on-off current ratio, the new device exhibits high on/off current ratio up to 10(6) for both n- and p-channel modes of operation. Moreover, the implantless feature and the ambipolar capability of the new device also result in extra low mask count for CMOS processes integration. These excellent device characteristics, coupled with its simple processing, make the new device very promising for future large-area electronic applications.
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    Self-aligned fabrication of thin-film transistors with field-induced drain
    (2002-08-01)
    Yu, CM
    ;
    Lin, HC
    ;
    Lin, CY
    ;
    Yeh, KL
    ;
    Huang, TY
    Thin-film transistor (TFT) devices with either a top or a bottom sub-gate were fabricated and characterized. The top sub-gate scheme allows the self-aligned formation of main-gate with respect to the sub-gate. On the other hand, the bottom sub-gate scheme features a self-aligned field-induced drain with a sidewall spacer located on its top to set the effective field-induction-drain (FID) length. Unlike the conventional TFTs, the FID serves to distribute the high drain electric field and thereby eliminates gate-induced drain leakage-like off-state leakage current. Superior device performance is realized with the bottom sub-gate structure. (C) 2002 Elsevier Science Ltd. All rights reserved.
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    Fabrication and characterization of Schottky barrier polysilicon thin-film transistors with excimer-laser crystallized channel
    (2003-04-01)
    Yeh, KL
    ;
    Lin, HC
    ;
    Tsai, RW
    ;
    Lee, MH
    ;
    Huang, TY
    Schottky barrier thin-film transistors (SB TFT) with field-induced drain (FID) have recently been demonstrated to exhibit ambipolar capability with low off-state leakage current. In this study, we investigate and compare the characteristics of poly-Si SB TFTs with channel layer prepared by excimer laser crystallization (ELC) and solid-phase crystallization (SPC). It is shown that the use of ELC could greatly improve the device characteristics, comparing to the SPC counterparts. Excellent device performance with steep subthreshold slope and on/off current ratio higher than 10(8) for both p- and n-channel operations are demonstrated on a single device with ELC channel. The effects of sub-gate bias, channel length, and channel offset length, on device characteristics are also explored.