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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Lin, Horng-ChihSubject: search.filters.subject.thin-film transistor

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Now showing 1 - 4 of 4
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    Fabrication and Characterization of Film Profile Engineered ZnO TFTs With Discrete Gates
    (2015-05-01)
    Lyu, Rong-Jhe
    ;
    Lin, Horng-Chih
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    By virtue of the film-profile engineering scheme and properly designed device structure, ZnO TFTs with discrete bottom gates and sub-micron channels were fabricated and characterized. In the fabrication, a suspended bridge constructed over the bottom gate is used to tailor the profile of subsequently deposited films. Superior electrical characteristics in terms of ultrahigh ON/OFF current ratio (similar to 10(10)), steep sub-threshold swing (66 similar to 108 mV/dec), and very low off-state leakage current are demonstrated with the fabricated devices. Effects of channel lengths on the device characteristics are also explored. Because of more effective shadowing of the depositing species with a longer suspended bridge, the deposited films become thinner at the central channel. As a result, the device shows more positive turn-on voltage and better subthreshold swing with increasing channel length.
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    Improving Electrical Performances of p-Type SnO Thin-Film Transistors Using Double-Gated Structure
    (2015-10-01)
    Zhong, Chia-Wen
    ;
    Lin, Horng-Chih
    ;
    Liu, Kou-Chen
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    p-type SnO thin-film transistors (TFTs) using a nominally symmetrical double-gated (DG) structure were studied in this letter. The top and bottom gates can be biased independently (single-gated mode) or jointly to switch the device (DG mode). For the latter operation, it is shown that ON current, subthreshold swing, and OFF-state current of the SnO TFT are all improved as compared with the operations when only one of the two gates is biased. As the device is operated under the DG mode, field-effect mobility of 6.54 cm(2)/V-s, high ON/OFF current ratio of >10(5), and subthreshold swing of 143 mV/decade are obtained. Moreover, the capability of the device in tuning its transfer characteristics under the single-gated operation with the bias applied to the opposite gate is also confirmed.
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    Film-Profile Engineered InGaZnO Thin-Film Transistors With Self-Aligned Bottom Gates
    (2015-08-01)
    Shie, Bo-Shiuan
    ;
    Lin, Horng-Chih
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We propose and demonstrate a method which combines film profile engineering (FPE) and a procedure of forming self-aligned bottom gates (SABGs) to fabricate InGaZnO thin-film transistors (TFTs). In the scheme, an ingenious etching procedure was implemented to form the final bottom gate self-aligned to the upper hardmask structure. The fabricated SABG devices show greatly reduced OFF-state leakage as compared with nonself-aligned ones, attributing to the reduction of gate-to-source/drain overlap areas which lowers both parasitic capacitance and gate leakage current. These merits benefit the operation of circuits consisted of TFTs implemented with FPE.
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    Impact of Residual Hardmask Wires on the Performance of Film-Profile-Engineered ZnO Thin-Film Transistors With Discrete Bottom Gates
    (2015-08-01)
    Lyu, Rong-Jhe
    ;
    Lin, Horng-Chih
    ;
    Huang, Tiao-Yuan
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Root cause for the anomalous degradation in the ON-current of film-profile-engineered ZnO thin-film transistors with discrete bottom gates, a new scheme proposed in our previous work, is investigated. Our findings indicate that the deposited source/drain (S/D) metal contact pads are disconnected owing to two TiN wires hung over the S/D regions, which are unintentionally formed during the fabrication of devices. The disconnected S/D metal contacts cause an increase in the S/D series resistance, and thus, the ON-current is degraded. Several ways for addressing this issue are proposed in this letter, including the simple thinning of gate electrode. As the undesirable TiN wires are eliminated, the devices demonstrate enhanced field-effect mobility and uniformity in performance.