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Now showing 1 - 9 of 9

Submicrometer p-Type SnO Thin-Film Transistors Fabricated by Film Profile Engineering Method
(2019-04-01)
Wu, Ming-Hung
;
Lin, Horng-Chih
;
Li, Pei-Wen
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
We reported the fabrication of submicrometer p-type tin monoxide (SnO) thin-film transistors (TFTs) with a channel length of 0.2 mu m for back-end-of-line applications using a film profile engineering (FPE) approach. Material analyses indicate that the as-deposited SnO films are amorphous, while be transformed to polycrystalline after a thermal annealing in oxygen ambient. Fabricated p-type SnO FPE-TFTs of a channel length of 0.2 mu m were manifested with ON/OFF current ratio higher than 105 and subthreshold slope of 320 mV/decade, superior to the data of submicrometer SnO devices ever reported. The extracted field-effect mobility is about 0.25 cm(2)/V.s. After ruling out the influence of source/drain series resistance, the intrinsic field-effect mobility is found to be about 1 cm(2)/V.s.
Fabrication of High-Performance Poly-Si Thin-Film Transistors With Sub-Lithographic Channel Dimensions
(2014-11-01)
Lee, Ko-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A method for fabrication of tri-gate polycrystalline silicon (poly-Si) transistors with short channel length and width is proposed and demonstrated without employing costly lithographic tools. Specifically, the method employs a spacer formation technique to extend source and drain regions so as to scale down the channel length below sub-lithographic dimension. Concurrently, the channel width is scaled down below sub-lithographic dimension by using a photoresist (PR) trimming technique. Our results show that the reduction in the planar channel width is essential for suppressing the short-channel effects. Finally, devices with channel length of 120 nm and planar channel width of 110 nm are demonstrated with superior electrical characteristics in terms of small subthreshold swing (146 mV/dec) and low drain-induced-barrier-lowing value (100 mV/V).
Characteristics of Planar Junctionless Poly-Si Thin-Film Transistors With Various Channel Thickness
(2013-03-01)
Lin, Horng-Chih
;
Lin, Cheng-I
;
Lin, Zer-Ming
;
Shie, Bo-Shiuan
;
Huang, Tiao-Yuan
N-type junctionless (JL) planar poly-Si thin-film transistors (TFTs), which contain an in situ heavily phosphorous-doped channel with thickness ranging from 8 to 12 nm, were fabricated and characterized. The devices exhibit superior current drive and good control over performance variability. From C-V characterization, the ionized dopant concentration in the channel is determined to be around 2 x 10(19) cm(-3) and the fixed charge density to be around -6 x 10(12) cm(-2). The negative fixed charge density is probably related to the segregation of phosphorous species at the oxide/channel interface. We also observed a reverse short-channel effect from the relationship between the threshold voltage and the channel length. One mechanism considering enhanced phosphorous segregation is proposed to explain this finding.
Low-Operating-Voltage Ultrathin Junctionless Poly-Si Thin-Film Transistor Technology for RF Applications
(2012-11-01)
Tsai, Tzu-I
;
Chen, Kun-Ming
;
Lin, Horng-Chih
;
Lin, Ting-Yao
;
Su, Chun-Jung
In this letter, for the first time, we experimentally investigate the radio-frequency (RF) characteristics and low-frequency noise (LFN) of n-type planar junctionless (JL) poly-Si thin-film transistors (TFTs). The fabricated JL devices show remarkable dc performance with good current drive and a high on-current/off-current ratio of 8 x 10(7). Furthermore, with the implementation of an in situ phosphorus-doped channel architecture and a salicide process, the JL device with a channel length of 0.4 mu m exhibits a cutoff frequency (f(t)) of 3.36 GHz and a maximum oscillation frequency (f(max)) around 7.37 GHz at a drain bias of 2 V. As far as LFN is concerned, the JL device shows approximately four orders of magnitude lower drain-current noise power spectral density (S-id) over conventional inversion-mode counterparts. These results demonstrate that the JL poly-Si TFT technique is promising for RF modules implemented in system-on-panel applications.
A Novel Scheme for Fabricating CMOS Inverters With Poly-Si Nanowire Channels
(2012-06-01)
Kuo, Chia-Hao
;
Lin, Horng-Chih
;
Lee, I-Che
;
Cheng, Huang-Chung
;
Huang, Tiao-Yuan
A novel complementary metal-oxide-semiconductor inverter with poly-Si nanowire channels is proposed and demonstrated in this letter. The scheme employs a clever tilted-angle implant process in the fabrication; therefore, the formation of the source and drain of both p-channel and n-channel devices requires only one lithographic step. The fabricated n-channel and p-channel field-effect transistors in the inverters show a high ON/OFF current ratio, an acceptable subthreshold swing, and a symmetric driving current, thus enabling the realization of excellent characteristics of the inverters.
Characteristics of n-Type Junctionless Poly-Si Thin-Film Transistors With an Ultrathin Channel
(2012-01-01)
Lin, Horng-Chih
;
Lin, Cheng-I
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this letter, we study the characteristics of n-type junctionless (JL) poly-Si thin-film transistors (TFTs) with an ultrathin and heavily phosphorous doped channel. The fabricated devices show excellent performance with a subthreshold swing of 240 mV/dec and an on/off current ratio of > 10(7). Moreover, the JL device shows 23 times increase in the ON-state current at a gate overdrive of 4 V as compared with the conventional control device with an undoped channel. The significant improvement in the current drive is ascribed to the inherently high carrier concentration contained in the channel of the JL device. These results evidence the great potential of the JL poly-Si TFTs for the manufacturing of future 3-D and flat-panel electronic products.
Fabrication and characterization of nanowire transistors with solid-phase crystallized poly-Si channels
(2006-10-01)
Lin, Horng-Chih
;
Lee, Ming-Hsien
;
Su, Chun-Jung
;
Shen, Shih-Wen
;
電子工程學系及電子研究所
The performance of thin-film transistors with a novel poly-Si nanowire channel prepared by solid-phase crystallization is investigated in this paper. As compared with conventional planar devices having self-aligned source/drain, the new devices show an improved ON-current per unit width and better control over the short channel effects. The major conduction mechanism of the OFF-state leakage is identified as the gate-induced drain leakage, and it is closely related to the source/drain implant condition and the unique device structure.
Gate-All-Around Junctionless Transistors With Heavily Doped Polysilicon Nanowire Channels
(2011-04-01)
Su, Chun-Jung
;
Tsai, Tzu-I
;
Liou, Yu-Ling
;
Lin, Zer-Ming
;
Lin, Horng-Chih
In this letter, we have investigated experimentally, for the first time, the feasibility of gate-all-around polycrystalline silicon (poly-Si) nanowire transistors with junctionless (JL) configuration by utilizing only one heavily doped poly-Si layer to serve as source, channel, and drain regions. In situ doped poly-Si material features high and uniform-doping concentration, facilitating the fabrication process. The developed JL device exhibits desirable electrostatic performance in terms of higher ON/OFF current ratio and lower source/drain series resistance as compared with the inversion-mode counterpart. Such scheme appears of great potential for future system-on-panel and 3-D IC applications.
Origins of Performance Enhancement in Independent Double-Gated Poly-Si Nanowire Devices
(2010-04-01)
Hsu, Hsing-Hui
;
Lin, Horng-Chih
;
Huang, Tiao-Yuan
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, we characterize and compare the characteristics of a poly-Si nanowire (NW) device with independent double-gated configuration under different operation modes. In the device, the tiny NW channels are surrounded by an inverted-T-shaped gate and a top gate. It is found that the device under double-gate (DG)mode exhibits significantly better performance with respect to the two single-gate (SG) modes, as indicated by a higher current drive than the combined sum of the two SG modes and a smaller subthreshold swing of less than 100 mV/dec. Origins of such improvement have been identified to be due to the elimination of the back-gate effect as well as an enhancement in the effective mobility with the DG operation.

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