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Use of Random Telegraph Signal as Internal Probe to Study Program/Erase Charge Lateral Spread in a SONOS Flash Memory
(2010)
Chou, Y. L.
;
Chiu, J. P.
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Ma, H. C.
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Wang, Tahui
;
Chao, Y. P.
A novel random telegraph signal (RTS) method is proposed to study the lateral spread of injected charges in program/erase of a NOR-type SONOS flash memory. The concept is to use RTS to extract an interface trap position and to detect a local potential variation near the trap due to injection of program/erase charges. By using this method, we find that CHISEL program has a broader charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band erase holes is observed directly from this method.
Modeling the Impact of Random Grain Boundary Traps on the Electrical Behavior of Vertical Gate 3-D NAND Flash Memory Devices
(2014-06-01)
Hsiao, Yi-Hsuan
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Lue, Hang-Ting
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Chen, Wei-Chen
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Chang, Kuo-Pin
;
Shih, Yen-Hao
The 3-D stacking of multiple layers of NAND using thin-film transistor (TFT) devices is widely accepted as the next step in continuing NAND Flash scaling. Low mobility and reliability problems are two well-known concerns regarding TFT devices. However, another important implication of using TFT devices is that the Vt variation induced by randomly distributed grain boundaries degrades the array performance. In this paper, an extensive TCAD simulation was conducted to systematically investigate how grain boundary generated traps affect NAND Flash devices. Minimizing the density of grain boundary traps is crucial for array performance. In addition, optimal gate control ability reduces the impact of grain boundaries. Thus, using double gate architecture in vertical gate 3-D NAND is favorable. Furthermore, when pitch is scaled in the future, device exhibiting smaller channel thickness should be used to increase the gate control.
V-t Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect
(2012-05-01)
Chung, Yueh-Ting
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Huang, Tzu-I
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Li, Chi-Wei
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Chou, You-Liang
;
Chiu, Jung-Piao
A V-t retention distribution tail in a multitime-program (MTP) silicon-oxide-nitride-oxide-silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced Delta V-t in NOR-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-lossinduced Delta V-t exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program V-t level in an MLC SONOS. In addition, we measure a V-t retention distribution in a 512-Mb MTP SONOS memory and observe a significant V-t retention tail. A numerical V-t retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured V-t retention distribution in a 512-Mb SONOS well. The observed V-t tail is realized mainly due to the percolation effect.
Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory
(2006-10-16)
Gu, Shaw-Hung
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Wang, Tahui
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Lu, Wen-Pin
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Ku, Yen-Hui Joseph
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Lu, Chih-Yuan
The authors propose a technique to extract a silicon nitride trap density from stress induced leakage current in a polycrystalline silicon-oxide-nitride-oxide-silicon flash memory cell. An analytical model based on the Frenkel-Poole emission is developed to correlate a nitride trap density with stress induced leakage current. The extracted nitride trap density is 7.0x10(12) cm(-2) eV(-1). They find that nitride trapped charges have a rather uniform distribution in an energy range of measurement (similar to 0.2 eV). (c) 2006 American Institute of Physics.
Numerical simulation of bottom oxide thickness effect on charge retention in SONOS flash memory cells
(2007-01-01)
Gu, Shaw-Hung
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Hsu, Chih-Wei
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Wang, Tahui
;
Lu, Wen-Pin
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Ku, Yen-Hui Joseph
In this paper, bottom-oxide thickness (T-bo) and program/erase stress effects on charge retention in SONOS Flash memory cells with FN programming are investigated. Utilizing a numerical analysis based on a multiple electron-trapping model to solve the Shockley-Read-Hall rate equations in nitride, we simulate the electron-retention behaviour in a SONOS cell with T-bo from 1,8 to 5.0 nm. In our model, the nitride traps have a continuous energy distribution. A series of Frenkel-Poole (FP) excitation of trapped electrons to the conduction band and electron recapture into nitride traps feature the transitions between the conduction band and trap states. Conduction band electron tunneling via oxide traps created by high-voltage stress and trapped electron direct tunneling through the bottom oxide are included to describe various charge leakage paths. We measure the nitride-charge leakage current directly in a large-area device for comparison. This paper reveals that the charge-retention loss in a high-voltage stressed cell, with a thicker bottom oxide (5 nm), exhibits two stages. The charge-leakage current is limited by oxide trap-assisted tunneling in the first stage and, then follows a 1/t time dependence due to the FP emission in the second stage. The transition time from the first stage to the second stage is related to oxide trap-assisted tunneling time but it prolonged by a factor.
Study of the gate-sensing and channel-sensing transient analysis method for monitoring the charge vertical location of SONOS-type devices
(2007-09-01)
Du, Pei-Ying
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Lue, Hang-Ting
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Wang, Szu-Yu
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Lai, Erh-Kun
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Huang, Tiao-Yuan
The gate-sensing and channel-sensing transient analysis method is studied in detail. This method introduces an additional gate-sensing capacitor to be compared with the conventional channel-sensing one. Sensing in both modes provides two equations that are suitable to solve for two variables-the charge density (Q) and the average charge vertical location (x). In this paper, the principle of this method is discussed in detail. Several factors that affect the measurement accuracy are also analyzed. The power of this method is demonstrated by program/erase cycling and data retention tests. This method is indeed a powerful tool for detailed understanding of trapping dynamics.
A Novel Random Telegraph Signal Method to Study Program/Erase Charge Lateral Spread and Retention Loss in a SONOS Flash Memory
(2011-03-01)
Ma, Huan-Chi
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Chou, You-Liang
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Chiu, Jung-Piao
;
Chung, Yueh-Ting
;
Lin, Tung-Yang
A novel random telegraph signal (RTS) method is proposed to characterize the lateral distribution of injected charge in program and erase states in a NOR-type silicon-oxide-nitride-oxide-silicon Flash memory. The concept of this method is to use RTS to extract an oxide trap position in the channel and then to use the trap and RTS as internal probe to detect a local channel potential change resulting from injected charge during program/erase. By using this method, the lateral width of the injected charge-induced channel potential barrier is shown to be around 20 nm in channel hot electron (CHE) program. Our method also confirms that Channel Initiated Secondary ELectron (CHISEL) program has a broader injected charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band tunneling erase holes is observed. Program-state V(t) retention loss models, charge vertical loss versus lateral migration, are reexamined by using this method. The polarity of a program-state charge distribution along the channel is explored within 10-20 program/erase cycles. Nitride charge vertical loss is verified by this method.
A study of gate-sensing and channel-sensing (GSCS) transient analysis method - Part II: Study of the intra-nitride behaviors and reliability of SONOS-type devices
(2008-08-01)
Du, Pei-Ying
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Lue, Hang-Ting
;
Wang, Szu-Yu
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Huang, Tiao-Yuan
;
Hsieh, Kuang-Yeu
For the first time, we can directly investigate the charge transport and intra-nitride behaviors of SONOS-type devices by exploiting the gate-sensing and channel-sensing (GSCS) method. Our results clearly indicate that for electron injection (+FN program), the electron centroid migrates from the bottom toward the nitride center, whereas for hole injection (-FN erase), holes first recombine with the bottom electrons and then gradually move upward. For the electron de-trapping processes under -V(G) stressing, the trapped electrons de-trap first from the bottom portion of nitride. We also develop a method to distinguish the electron de-trapping and hole injection erasing methods by comparing the erasing current density (J) versus the bottom oxide electric field (E). At short-term high-temperature baking, the electrons move from the top portion toward the bottom portion, and this intra-nitride transport becomes more significant for a thicker nitride. On the other hand, after long-term baking, the charge loss mainly comes from the bottom portion of nitride.
A Novel Hot-Electron Programming Method in a Buried Diffusion Bit-Line SONOS Memory by Utilizing Nonequilibrium Charge Transport
(2009-02-01)
Wang, Tahui
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Tang, Chun-Jung
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Li, C. -W.
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Lee, Chih Hsiung
;
Ou, T. -F
We propose a new hot-electron programming method with a low drain-to-source voltage in a buried-diffusion (BD) bit-line SONOS memory array. In this method, channel electrons are preaccelerated in a cell preceding a program cell. For a small bit-line width, some energetic electrons will traverse an n(+) BD region and enter a program cell with residual energy due to nonequilibrium transport. Our measurement result shows that this residual energy can significantly enhance hot-electron programming efficiency even at a V(ds) of 2.5 V. The concept of this method is verified by means of a Monte Carlo analysis. Our study shows that this method is more effective as a bit-line width reduces.
Pulse-IV Characterization of Charge-Transient Behavior of SONOS-Type Devices With or Without a Thin Tunnel Oxide
(2009-04-01)
Du, Pei-Ying
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Lue, Hang-Ting
;
Wang, Szu-Yu
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Huang, Tiaci-Yuan
;
Hsieh, Kuang-Yeu
The transient behavior of SONOS-type devices was investigated for the first time using pulse-IV technique. Three kinds of SONOS devices are studied: SONS (without top oxide), SONoS (with a thin top oxide), and SoNOS (with a thin bottom oxide). Devices with or without a thin tunnel oxide were able to provide very fast charge injection/detrapping, but their charge-transient behavior cannot be accurately monitored by conventional DC-IV method. By using specific pulse-IV setup for memory, we can measure the drain current response immediately after programming and erasing, as well as the fast charge relaxation under various reliability tests. The program and erase transient behavior shows that all devices are easily programmed and erased within 1 mu s at low gate voltages (< 6 V). Moreover, SONS shows the fastest program and erase speeds because of the absence of tunnel oxide, and silicon nitride has very low barrier height that offers fast injection. We have also examined the charge relaxation under various field and temperature conditions and found that the charge loss mainly came from external charge injection during retention, not from detrapping through thermionic emission.

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