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2.4-GHz Tunable Miniature CMOS Active Bandpass Filter With Two Transmission Zeros Using Lumped Stepped-Impedance Ring Resonator
(2018-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Chien, Hsieh-Hsiu Chang
;
Huang, Guo-Wei
;
電機工程學系
This paper demonstrates a small-size 2.4-GHz CMOS active bandpass filter with two transmission zeros using a lumped stepped-impedance ring resonator. To obtain low insertion loss and small size, four high-Q active inductors using 0.18 gm CMOS transistors only are employed in the design. The measured insertion loss is 2.9-dB at 2.4 GHz center frequency with two transmission zeros located at 2.1 GHz and 3.1 GHz, respectively. By tuning the bias currents of active inductors, the center frequency has 1.4 GHz tuning range and the 1-dB bandwidth can be adjusted in the range of 190 MHz to 260 MHz. The demonstrated active filter occupies a small chip area of 0.47 mm x 0.33 mm excluding I/O pads and has 24 dB noise figure. Thus, an active filter with a preceding two-stage common-source LNA for suppression of noise of the active filter is also demonstrated and the resulting LNA + active filter has 6 dB noise figure. The power consumption of the active filter core and the LNA core is 9 mW and 7.2 mW, respectively.
SBD Layout Optimization with Effect of N-well to p-Substrate pn Junctions in 0.18 mu m CMOS Process
(2016-01-01)
Chang, Wei-Ling
;
Meng, Chinchun
;
Huang, Guo-Wei
;
電機工程學系
;
Department of Electrical and Computer Engineering
The effect of layout on silicon SBD in CMOS process is studied in this paper. The size of anode area not only affects the series resistance and SBD junction capacitance but also causes serious parasitic effect from cathode to the p-substrate. Typically, an SBD of a small unit anode has a better cut-off frequency than that of a large unit anode. The cutoff frequency of a small anode Schottky diode is about 700 GHz in a standard 0.18 mu m CMOS process. However, a SBD with a small unit anode is prone to the effect of p-substrate to N-well pn junction capacitor. This paper has characterized SBDs of different anode sizes with bottom and side-wall effect of p-substrate to N-well to select an optimal unit-anode area by reducing the substrate effect and providing sufficient f(T) for high frequency applications.
Flicker Noise and Power Performance of CMOS Gilbert Mixers Using Static and Dynamic Current-Injection Techniques
(2010-01-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Chien, Hsin-I
;
Lu, Hsi-Liang
;
Syu, Jin-Siang
The Gilbert Mixers using static and dynamic current-injection techniques are all implemented in 0.13 mu m CMOS technology. As the experimental results, the dynamic injection technique has higher conversion gain, less sensitivity to current injection, smaller required LO power, better noise figure and lower flicker noise when the transistor size and biasing condition are the same as that of static injection technique for a fair comparison.
A Chebyshev-Response Step-Impedance Phase-Inverter Rat-Race Coupler Directly on Lossy Silicon Substrate and Its Gilbert Mixer Application
(2011-04)
Wei, Hung-Ju
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Chang, Chia-Hung
;
電機工程學系
This paper focuses on the analysis and the design methodology of the step-impedance phase-inverter rat-race coupler on a silicon-based process. The issues of impedance limitation and bandwidth are discussed in detail. Our proposed concept utilizes a high silicon dielectric constant, phase-inverter structure, step-impedance technique, and Chebyshev response to make the rat-race coupler more compact (similar to 64 reduction) and highly balanced over a wide operating bandwidth. Moreover, the inter-digital coplanar stripline used in the step-impedance section effectively reduces the characteristic impedance of the transmission line for large size shrinkage and insertion-loss reduction. The demonstrated step-impedance rat-race coupler directly on silicon substrate has 6- similar to 7-dB insertion loss from 5 to 15 GHz and small variations in amplitude/phase balance. Compared with our previous work, the proposed rat-race coupler achieves a 3-dB improvement in the insertion loss. Thus, a 0.13-mu m CMOS Gilbert down-converter with a miniature phase-inverter rat-race coupler at the RF path for wideband single-to-differential signal conversion achieves a noise figure of 16 dB.
A Chebyshev-Response Step-Impedance Phase-Inverter Rat-Race Coupler Directly on Lossy Silicon Substrate and Its Gilbert Mixer Application
(2011-04)
Wei, Hung-Ju
;
Meng, Chinchun
;
Yu, Sheng-Wen
;
Chang, Chia-Hung
;
電機工程學系
This paper focuses on the analysis and the design methodology of the step-impedance phase-inverter rat-race coupler on a silicon-based process. The issues of impedance limitation and bandwidth are discussed in detail. Our proposed concept utilizes a high silicon dielectric constant, phase-inverter structure, step-impedance technique, and Chebyshev response to make the rat-race coupler more compact (similar to 64 reduction) and highly balanced over a wide operating bandwidth. Moreover, the inter-digital coplanar stripline used in the step-impedance section effectively reduces the characteristic impedance of the transmission line for large size shrinkage and insertion-loss reduction. The demonstrated step-impedance rat-race coupler directly on silicon substrate has 6- similar to 7-dB insertion loss from 5 to 15 GHz and small variations in amplitude/phase balance. Compared with our previous work, the proposed rat-race coupler achieves a 3-dB improvement in the insertion loss. Thus, a 0.13-mu m CMOS Gilbert down-converter with a miniature phase-inverter rat-race coupler at the RF path for wideband single-to-differential signal conversion achieves a noise figure of 16 dB.
E-Band RF-to-DC Converter Using Schottky Diode in 0.18-mu m CMOS Technology
(2016)
Chang, Wei-Ling
;
Meng, Chinchun
;
Fu, Tzu-Chien
;
Huang, Guo-Wei
;
電機工程學系
This paper demonstrates a millimeter-wave RF-to-DC converter based on Schottky-barrier diodes using 0.18-mu m CMOS technology. The Schottky-barrier diode has a cutoff frequency of 400 GHz and a low turn-on voltage of 0.3 V. In the RF-to-DC quadrupler, the difference in turn-on voltages between the Schottky-barrier diode and n-well to p-substrate parasitic pn junction prevents the pn junction from turning on with an effect similar to the Schottky diode clamp in Schottky TTL circuits. The input matching has a better than 10 dB return loss from 50 GHz to 100 GHz. The RF-to-DC quadrupler generates a 3.15 V DC voltage at 84 GHz.
5-6 GHz CMOS Low-Noise Direct Conversion Receiver Using a Differential RF VGA with a Differential Inductor Load
(2016)
Chang, Wei-Ling
;
Meng, Chinchun
;
Chang, Chih-Kai
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
A low-noise low-power direct conversion receiver with a differential RF VGA is demonstrated using 0.18um CMOS technology. A topology that uses a differential inductor load for a differential RF VGA is employed for the single-to-differential conversion. Since the common-mode rejection ratio of a differential variable gain amplifier is increased by the mutual magnetic coupling in a differential inductor load, this work achieves noise floor less than 5 dB covering the 5-6 GHz band. Moreover, the conversion gain is around 50 dB and the total current consumption is 4.75 mA at 1.8 V supply voltage.
60-GHz Dual-Conversion Down-/Up-Converters Using Schottky Diode in 0.18 mu m CMOS Process: An Alternative Approach for Millimeter-Wave Transceiver (Invited Talk)
(2012)
Meng, Chinchun
;
Chang, Mau-Chung Frank
;
電機資訊學士班
;
Undergraduate Honors Program of Electrical Engineering and Computer Science
An alternative approach for 60 GHz transceiver is proposed in this invited paper. The proposed 60 GHz transceiver has GaAs LNA/PA at the front end and the rest of the transceiver is realized in a low-cost foundry CMOS technology with the help of Schottky diode. The 60 GHz transceiver by 65-nm CMOS technology did not show adequate performance and suffers from high R&D cost because of the expensive photo masks while a transceiver based on the GaAs technology is plagued with the high manufacturing cost even though the noise figure of LNA and PAE of PA are good. The recent demonstrated down-/up-converters using Schottky diode in 0.18 mu m CMOS process by our group sheds light on this alternative approach for millimeter-wave transceivers.
.2.4 GHz divide-by-256 similar to 271 single-ended frequency divider in standard 0.35-mu m CMOS technology
(2005)
Tseng, Sheng-Che
;
Meng, Chinchun
;
Li, Shao-Yu
;
Su, Jen-Yi
;
Huang, Guo-Wei
This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in standard 0.35-um 2P4M CMOS technology. This frequency divider is composed of a synchronous CML divide-by4/5 prescaler, an asynchronous TSPC TFF divide-by-64 divider and digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 MHz to 2.9 GHz. Most of input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.20.7 mm(2).
Single-ended frequency divider with moduli of 256-271
(2006-10-01)
Tseng, Sheng-Che
;
Meng, Chinchun
;
Li, Shao-Yu
;
Su, Jen-Yi
;
Huang, Guo-Wei
This paper demonstrates a low-cost 2.4 GHz single-ended frequency divider with the divide-by-value from 256 to 271 in the standard 0.35-mu m 2P4M CMOS technology. This frequency divider is composed of a synchronous current mode logic divide-by-4/5 prescaler, an asynchronous true single-phase-clock toggle flip-flops divide-by-64 divider, and a digital control circuitry. This proposed divider is single-ended and compatible to the single-ended low-phase-noise Colpitts VCO. The operating frequency range of the divider is from 400 to 2.9 GHz. Most of the input sensitivity levels are about -10 dBm and the lowest level is -25 dBm at 2.4 GHz. Its core power consumption is about 28 mW. The chip size is 1.2 X 0.7 mm(2). (C) 2006 Wiley Periodicals, Inc.

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