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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Su, Pin

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Now showing 1 - 10 of 152
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    A Comprehensive Kinetical Modeling of Polymorphic Phase Distribution of Ferroelectric-Dielectrics and Interfacial Energy Effects on Negative Capacitance FETs
    (2019-01-01)
    Tang, Y-T
    ;
    Fang, C-L
    ;
    Kao, Y-C
    ;
    Modolo, N.
    ;
    Su, C-J
    This paper clarifies for the first time the origin of ferroelectricity in the Negative Capacitance Field-Effect Transistors (NCFETs) by molecular dynamics (MD) simulation. MD simulation considering atomic interactions between all atoms enables accurate predictions for the microstructure even at all interfaces. By incorporating the results from MD simulations into a kinetic model, it is able to predict the conditions of crystallization and phase transition during RTP and cooling processes that govern ferroelectricity in FETs. Our simulation reveals that the comparable interfacial energy between o- and t- phase, and in-plane tensile stress from metal capping or interfacial layers (ILs) enable more phase transition from t- to o-phase, and more ferroelectricity in NCFETs. Finally, design methodology to maintain the electric variation of NCFETs is also proposed
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    Electrostatic Integrity in Negative-Capacitance FETs - A Subthreshold Modeling Approach
    (2019-01-01)
    Su, Pin
    ;
    You, Wei-Xiang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    Using an analytical subthreshold potential model, this paper shows that the negative-capacitance FinFET (NC-FinFET) inherently possesses a superior electrostatic integrity than the baseline FinFET. Taking into account the spacer induced distributed charges in our subthreshold model, we demonstrate that an adequate spacer design can be utilized to further enhance the NC effect and the electrostatic integrity for NC-FinFETs. This may serve as a way to extend the FinFET scaling.
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    Variability Analysis for Ferroelectric FET Nonvolatile Memories Considering Random Ferroelectric-Dielectric Phase Distribution
    (2020-03-01)
    Liu, You-Sheng
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper investigates the impact of the random ferroelectric-dielectric (FE-DE) phase distribution on the memory window (MW) of the ferroelectric field-effect transistor (FeFET) nonvolatile memory (NVM) with the aid of TCAD atomistic simulations. Our study indicates that the DE path from source to drain is detrimental to the MW, and down-scaling the gate length substantially increases the probability of forming DE path and the variability in the MW. In addition, the MW variability for scaled FeFET devices can be mitigated by reducing the grain size, even under the same grain-to-channel area ratio. Besides, when down-scaling the insulator thickness to increase the MW, the increased MW variability due to the random FE-DE grains needs to be considered. Our study may provide insights for future scaling of FeFET NVMs.
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    A New 8T Hybrid Nonvolatile SRAM With Ferroelectric FET
    (2020-01-01)
    You, Wei-Xiang
    ;
    Su, Pin
    ;
    Hu, Chenming
    ;
    電子工程學系及電子研究所
    ;
    國際半導體學院
    This paper proposes a new 8T nonvolatile SRAM (nvSRAM) cell employing ULP FinFETs and ferroelectric FinFETs to enable energy-efficient and low-latency store/recall operations. Different from other types of nvSRAM requiring additional circuitry or nonvolatile memories connected to a standard 6T SRAM cell to achieve nonvolatility, the proposed hybrid nvSRAM cell reduces the area penalty by embedding the nonvolatile ferroelectric FinFETs in a 6T SRAM cell without sacrificing the cell stability, read/write performance and power consumption.
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    Investigation of Inversion Charge Characteristics and Inversion Charge Loss for InGaAs Negative-Capacitance Double-Gate FinFETs Considering Quantum Capacitance
    (2020-01-01)
    Huang, Shih-En
    ;
    Lin, Shih-Han
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    This paper investigates the inversion charge characteristics and quantum-capacitance induced inversion charge loss for In0.53Ga0.47As negative-capacitance FinFETs (NC-FinFETs) using theoretical calculation corroborated with numerical simulation. Our study indicates that, the boost of inversion charges due to negative capacitance increases with increasing remnant polarization P-r. In addition, the inversioncharge boosting for the In0.53Ga0.47As device is significantly larger than that of the Si (110) device due to the step-like inversion capacitance characteristic stemming from the 2D density-of-states of the In0.53Ga0.47As device. In other words, the quantum-capacitance induced inversion-charge loss for III-V channel can be mitigated in NCFETs.
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    Device Structural Effects, SPICE Modeling and Circuit Evaluation for Negative-Capacitance FETs
    (2019-01-01)
    Su, Pin
    ;
    You, Wei-Xiang
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
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    Evaluation of 2D Negative-Capacitance FETs for Low-Voltage SRAM Applications
    (2019-01-01)
    Tseng, Kuei-Yang
    ;
    You, Wei-Xiang
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work, we comprehensively evaluate and analyze the stability and performance of 6T SRAM cells using 2D MFIS-type negative capacitance FETs (2D-NCFETs) based on the IRDS 2030 node with 10-nm gate length. Our results indicate that 2D-NCFETs possess better RSNM than the 2D-FET counterpart under low supply voltages. Our study also shows that 2D-NCFETs have better WSNM except for V-DD = 0.2V due to the existence of hysteresis loop in write curve during write operation. By using write-assist circuits or back-gating techniques, we demonstrate that the WSNM of 2D-NCFETs can be significantly improved. We further analyze the performance of read and write operations, and 2D-NCFETs have been found to possess better performance than 2D-FETs.
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    Impact of Multi-Domain Interaction on ON-State Characteristics of MFIS-Type 2D Negative-Capacitance FETs
    (2019-01-01)
    Lu, Po-Sheng
    ;
    Lin, Chia-Chen
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this work, with the aid of segmented SPICE simulation, we investigate the impact of multi-domain interaction on MFIS-type 2D Negative-Capacitance FETs with emphasis on the ON-state characteristics. Our study indicates that the multi-domain interaction enhances the lateral electric field for the MFIS device, leading to a higher ON-current. In addition, the multi-domain interaction increases the saturation drain voltage of the MFIS device due to the rise of the internal voltage near the drain-side. Our study also suggests that the negative differential resistance (NDR) effect present in MFIS devices may result from the strong domain interaction in addition to negative DIBL.
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    Investigation of Ferroelectric Granularity for Double-Gate Negative-Capacitance FETs Considering Position and Number Fluctuations
    (2019-01-01)
    Fan, Che-Lun
    ;
    Tseng, Kuei-Yang
    ;
    Liu, You-Sheng
    ;
    Su, Pin
    ;
    電子工程學系及電子研究所
    Using TCAD atomistic simulation, this work investigates the ferroelectric layer granularity of double-gate (DG) negative-capacitance FETs (NCFET) by considering both position and number fluctuations. Our study indicates that the impacts of the ferroelectric ratio on threshold voltage (V-T) and subthreshold swing (SS) variations exhibit non-monotonic characteristics, and it is important to include the number fluctuation of the ferroelectric grain to accurately account for the overall variation. In addition, smaller grain size not only reduces the V-T and SS variations, but also improves the mean value of the subthreshold swing.
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    Benchmarking of Monolayer and Bilayer Two-Dimensional Transition Metal Dichalcogenide (TMD) Based Logic Circuits and 6T SRAM Cells
    (2016-01-01)
    Yu, Chang-Hung
    ;
    Su, Pin
    ;
    Chuang, Ching-Te
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    We evaluate and benchmark the performance of logic circuits and stability/performance of 6T SRAM cells using monolayer and bilayer TMD devices based on ITRS 2028 (5.9nm) technology node. For the performance benchmarking of logic circuits, the tradeoff between electrostatic integrity ( monolayer favored) and carrier mobility (bilayer favored), and the issues regarding the uncertainties in the mobility ratio and source/drain series resistance, the underlap device design, and the off-current spec., etc. are comprehensively addressed. In the evaluation of SRAM cells, the cell immunity to random variations is focused. Besides, the impact of high R-SD of TMD materials on RSNM variability is also investigated. The source/drain underlap design is shown to alleviate the larger variability of bilayer SRAM cells. Finally, with superior electrostatics and immunity to random variations, the monolayer TMD devices are favored for low-power logic and SRAM applications; while the bilayer devices, with higher carrier mobility, are more suitable for high-performance logic and SRAM applications.