<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

Filters

2012 - 201925

Settings

🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Su, Yu-Ting

Search Results

Now showing 1 - 10 of 25
  • Thumbnail Image
    Item type:Item,
    Overcoming Limited Resistance in 1T1R RRAM Caused by Pinch-Off Voltage During Reset Process
    (2019-11-01)
    Zheng, Hao-Xuan
    ;
    Chen, Min-Chen
    ;
    Chang, Ting-Chang
    ;
    Su, Yu-Ting
    ;
    Chen, Wen-Chung
    This article explains the difference in the reset processes between single RRAM and 1T1R RRAM structures. In the single RRAM, as the reset voltage increases, the off-state resistance increases. This is a normal RRAM operation. However, in the 1T1R structure, the reset voltage increases while the OFF-state resistance does not increase. This may be caused by either current or voltage being insufficient to switch the RRAM to its higher resistance state. The measurements of real voltage indicate that the insufficient voltage is in fact the main cause. For the 1T1R RRAM structure, if it is to be reset to a higher resistance state, it is best done by increasing the gate voltage to increase the OFF-state resistance. Therefore, we provide a method to reduce the misjudgment in the array, and it would be beneficial for the development of high-density memory.
  • Thumbnail Image
    Item type:Item,
    Efficient Implementation of Boolean and Full-Adder Functions With 1T1R RRAMs for Beyond Von Neumann In-Memory Computing
    (2018-10-01)
    Wang, Zhuo-Rui
    ;
    Li, Yi
    ;
    Su, Yu-Ting
    ;
    Zhou, Ya-Xiong
    ;
    Cheng, Long
    In-memory computing architecture is an emerging revolutionary computing paradigm that can break the von Neumann bottleneck. Computing methodology and circuit codesign using the CMOS compatible 1T1R resistive random access memory (RRAM) integration structure is presented in this paper. Functionally complete Boolean logic and arithmetic functions are experimentally demonstrated. With a single 40-nm CMOS process 1T1R unit, each of the 16 binary logics can be realized in two logic steps with an additional readout step for cascading, which shows functional reconfiguration and low computational complexity. Up to 10(7) cycles of NAND and XOR logic operations are performed to validate the correctness and reliability. Moreover, several fundamental adder circuits are designed and experimentally demonstrated in 1T1R devices as the proof of concept of the 1T1R computing architecture. The adders proposed in this paper include a ripple-carry adder and its optimized design and a carry-select adder, which all show promising advantages in nonvolatility, computation speed, and circuit area. This paper reports the most complex yet efficient RRAM-based 8-bit addition function experimentally so far and lays a solid foundation for constructing the future in-memory computing architecture.
  • Thumbnail Image
    Item type:Item,
    The influence of temperature on set voltage for different high resistance state in 1T1R devices
    (2019-02-01)
    Tan, Yung-Fang
    ;
    Su, Yu-Ting
    ;
    Chen, Min-Chen
    ;
    Chang, Ting-Chang
    ;
    Tsai, Tsung-Ming
    HfO2-based 1T1R is researched in this paper. The on-off ratio is an important electrical characteristic of RRAM, with a larger on-off ratio being preferable. However, temperature also affects the set process when operating RRAM. This study finds that the set process has different sensitivities to temperature at different high resistance states (HRSs). The set voltage of the higher HRS decreases with increasing temperature, while in the lower HRS, set voltage is independent of temperature. From the result, the lower HRS is better for RRAM because it is stable at different temperatures. (C) 2019 The Japan Society of Applied Physics
  • Thumbnail Image
    Item type:Item,
    Stabilizing Resistive Switching Characteristics by Inserting Indium-Tin-Oxide Layer as Oxygen Ion Reservoir in HfO2-Based Resistive Random Access Memory
    (2019-03-01)
    Chen, Po-Hsun
    ;
    Su, Yu-Ting
    ;
    Chang, Fu-Chen
    ;
    電子物理學系
    ;
    Department of Electrophysics
    This paper investigates the issues of oxygen accumulation and variation in the high-resistance state of HfO2-based resistive random access memory (RRAM), with improvement attained by inserting a thin oxygen-vacancy-rich layer of indium-tin-oxide (ITO) film. By acting as the oxygen ion reservoir, this ITO thin film on the TiN electrode can further stabilize resistance switching (RS) characteristics. In terms of reliability, ac endurance, and retention tests confirm stable RS characteristics for the Pt/HfO2/ITO/TiN device. Finally, a conducting model was proposed to explain the influence of the ITO thin layer and clarify the physical mechanism of electrical improvements.
  • Thumbnail Image
    Item type:Item,
    Attaining resistive switching characteristics and selector properties by varying forming polarities in a single HfO2-based RRAM device with a vanadium electrode
    (2017-07-07)
    Lin, Chih-Yang
    ;
    Chen, Po-Hsun
    ;
    Chang, Ting-Chang
    ;
    Chang, Kuan-Chang
    ;
    Zhang, Sheng-Dong
    This study proposes a method for a HfO2-based device to exhibit both resistive switching (RS) characteristics as resistive random access memory (RRAM) and selector characteristics by introducing vanadium (V) as the top electrode. This simple V/HfO2/TiN structure can demonstrate these two different properties depending on forming polarities. The RS mechanism is activated by a positive forming bias. In contrast, the selector property is induced by a negative forming bias. The material analyses firstly confirm the existence of V in the top electrode. Then the electrical measurements for the same V/HfO2/TiN structures but with different forming polarities were carried out to further investigate their DC sweeping characteristics to act as either a selector or RRAM device. Furthermore, reliability tests for both selector and RRAM devices were also conducted to confirm their switching stabilities. Finally, current fitting methods and temperature influence experiments were performed to investigate the carrier transport mechanisms. Finally, physical models were proposed to illustrate the selector property and RS mechanism for selector and RRAM devices, respectively. This simple device structure with its easy operating method accomplishes a significant advancement of devices combining both selector properties and RRAM for remarkable real applications in the near future.
  • Thumbnail Image
    Item type:Item,
    Nonvolatile reconfigurable sequential logic in a HfO2 resistive random access memory array
    (2017-05-28)
    Zhou, Ya-Xiong
    ;
    Li, Yi
    ;
    Su, Yu-Ting
    ;
    Wang, Zhuo-Rui
    ;
    Shih, Ling-Yi
    Resistive random access memory (RRAM) based reconfigurable logic provides a temporal programmable dimension to realize Boolean logic functions and is regarded as a promising route to build non-von Neumann computing architecture. In this work, a reconfigurable operation method is proposed to perform nonvolatile sequential logic in a HfO2-based RRAM array. Eight kinds of Boolean logic functions can be implemented within the same hardware fabrics. During the logic computing processes, the RRAM devices in an array are flexibly configured in a bipolar or complementary structure. The validity was demonstrated by experimentally implemented NAND and XOR logic functions and a theoretically designed 1-bit full adder. With the trade-off between temporal and spatial computing complexity, our method makes better use of limited computing resources, thus provides an attractive scheme for the construction of logic-in-memory systems.
  • Thumbnail Image
    Item type:Item,
    Effect of charge quantity on conduction mechanism of high-and low-resistance states during forming process in a one-transistor-one-resistor resistance random access memory
    (2017-05-01)
    Wu, Cheng-Hsien
    ;
    Chang, Ting-Chang
    ;
    Tsai, Tsung-Ming
    ;
    Chang, Kuan-Chang
    ;
    Chu, Tian-Jian
    The forming process is a necessary and irreversible process to activate the resistance switching behavior in a resistance random access memory (RRAM) device. However, during the forming process, an overshoot current leads to device damage and causes inferior resistance switching characteristics; consequently, the process is considered to be a key factor in device degradation. In this paper, we find that a discontinuous conduction path can be formed by a pulse forming process such that the operation current can be reduced. We further investigate how the charge quantity during the forming process affects the carrier conduction mechanism of HRS, with all experiments and results demonstrated on onetransistor- one-resistor (1T1R) devices. (C) 2017 The Japan Society of Applied Physics
  • Thumbnail Image
    Item type:Item,
    Reducing Forming Voltage by Applying Bipolar Incremental Step Pulse Programming in a 1T1R Structure Resistance Random Access Memory
    (2018-06-01)
    Zheng, Hao-Xuan
    ;
    Chang, Ting-Chang
    ;
    Xue, Kan-Hao
    ;
    Su, Yu-Ting
    ;
    Wu, Cheng-Hsien
    This letter introduces a method of using bipolarity bias voltages in the forming process to effectively reduce the forming voltage of a one-transistor and one-resistance random access memory device. A bipolar incremental-step-pulse programming process is applied, and a complete operation pulse for the forming process is described. This method reduces forming voltage without any cost to the device performance, and the device maintains good reliability. The likely physical mechanism of this bipolar operation is also presented based on the measured electrical characteristics.
  • Thumbnail Image
    Item type:Item,
    Suppression of endurance degradation by applying constant voltage stress in one-transistor and one-resistor resistive random access memory
    (2017-01-01)
    Su, Yu-Ting
    ;
    Chang, Ting-Chang
    ;
    Tsai, Tsung-Ming
    ;
    Chang, Kuan-Chang
    ;
    Chu, Tian-Jian
    In this letter we demonstrate an operation method that effectively suppresses endurance degradation. After many operations, the off-state of resistance random access memory (RRAM) degrades. This degradation is caused by reduction of active oxygen ions participating in the set process, as determined by current fitting of current-voltage (I-V) curves obtained from the endurance test between the interval of seventy to one hundred million operations. To address this problem, we propose the application of constant voltage stress after every five million operations during the endurance test. The experimental result shows that this method can maintain oxygen ions at the proper depth in the electrode and improve RRAM reliability. (c) 2017 The Japan Society of Applied Physics
  • Thumbnail Image
    Item type:Item,
    Functionally Complete Boolean Logic in 1T1R Resistive Random Access Memory
    (2017-02)
    Wang, Zhuo-Rui
    ;
    Su, Yu-Ting
    ;
    Li, Yi
    ;
    Zhou, Ya-Xiong
    ;
    Chu, Tian-Jian
    Nonvolatile stateful logic through RRAM is a promising route to build in-memory computing architecture. In this letter, a logic methodology based on 1T1R structure has been proposed to implement functionally complete Boolean logics. Arbitrary logic functions could be realized in two steps: initialization and writing. An additional read step is required to read out the logic result, which is in situ stored in the nonvolatile resistive state of the memory. Cascade problem in building larger logic circuits is also discussed. Our 1T1R logic device and operation method could be beneficial for massive integration and practical application of RRAM-based logic.