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5-6 GHz 9.4 mW CMOS Direct-Conversion Passive-Mixer Receiver With Low-Flicker-Noise Corner
(2012-01-01)
Hsiao, Yu-Chih
;
Meng, Chinchun
;
Syu, Jin-Siang
;
Lin, Chung-Yo
;
Wong, Shyh-Chyi
This paper demonstrates a low-power and low-flicker-noise direct-conversion receiver using double-balanced passive mixer. The deep-n-well vertical-NPN bipolar junction transistor is placed as at the input stage of the IF amplifier to reduce the flicker noise in the 0.18 um standard CMOS process. As a result, conversion gain achieves 50-dB gain when the LO power is 10 dBm and the noise figure is 7-dB at 100 kHz. The totally power consumption is 9.4 mW at 1.8 V voltage supply.
2-GHz 1.35-dB NF pHEMT Single-Voltage-Supply Process-Independent Low-Noise Amplifier
(2018-01-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Yang, Chun
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
A 2-GHz single-voltage-supply 0.15-mu m depletion-mode (D-mode) pseudomorphic high electron-mobility transistor (pHEMT) low-noise amplifier (LNA) is demonstrated with a proposed process-independent self-biasing scheme. The current-reused technique is also employed to achieve a common-source common-drain two-stage LNA under a dc current of 10.85 mA at a 3-V supply. As a result, the proposed LNA achieves 20-dB power gain and 1.35-dB noise figure (NF) at 2 GHz while the minimum NF=1.3 dB occurs at 2.4 GHz.
Programmable-Gain Constant-IF-Bandwidth SiGe BiCMOS Upconversion Micromixer at 2.4/5.8 GHz Using Current-Mode Approach
(2017-01-01)
Syu, Jin-Siang
;
Chang, Wei-Ling
;
Meng, Chinchun
;
Lin, Yi-Chen
;
Huang, Guo-Wei
A 2.4/5.8-GHz dual-band programmable-gain upconverter with a constant IF bandwidth is demonstrated using 0.35-mu m SiGe BiCMOS technology. Using a current-mode design approach, the input IF bandwidth remains the same at different gain settings. A dual-band LC current combiner is used at the mixer RF output to combine differential signals to a single-ended one at two bands. Then, a wideband amplifier is cascaded after the dual-band mixer. The demonstrated upconverter achieves maximum gain of -4/-3 dB at 2.4/5.8 GHz, respectively. In addition, four gain steps with 5-dB gain difference between each step are controlled by a two-bit digital circuit. The total current consumption is 26 mA at a 4-V supply.
Flicker Noise and Power Performance of CMOS Gilbert Mixers Using Static and Dynamic Current-Injection Techniques
(2010-01-01)
Wei, Hung-Ju
;
Meng, Chinchun
;
Chien, Hsin-I
;
Lu, Hsi-Liang
;
Syu, Jin-Siang
The Gilbert Mixers using static and dynamic current-injection techniques are all implemented in 0.13 mu m CMOS technology. As the experimental results, the dynamic injection technique has higher conversion gain, less sensitivity to current injection, smaller required LO power, better noise figure and lower flicker noise when the transistor size and biasing condition are the same as that of static injection technique for a fair comparison.
Ka-Band pHEMT Quadrupler with Injection and Extraction from Oscillator Frequency Doubling Points
(2014-01-01)
Chang, Wei-Ling
;
Meng, Chinchun
;
Syu, Jin-Siang
;
Wu, Yan-Feng
;
Huang, Guo-Wei
A Ka-band injection-locked quadrupler MMIC is demonstrated using 0.15-mu m pseudomorphic high electron mobility transistor (pHEMT) technology. pHEMT technology is suitable to the millimeter wave quadrupler by using the topology of high-order sub-harmonic injection lock based on a cross-coupled oscillator. Furthermore, thanks to the semi-insulating GaAs substrate, it is easy to implement microwave/millimeter wave passive components to achieve accurate balanced signals. As a result, the measured output power of the quadrupler is 8 dBm for frequency of 30 GHz and the locking bandwidth reaches 300 MHz.
9.9-mA 5-6 GHz CMOS Sub-Harmonic Direct-Conversion Receiver Using Deep N-Well BJT
(2014-01-01)
Chang, Wei-Ling
;
Meng, Chin-Chun
;
Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power sub-harmonic direct-down receiver is demonstrated using 0.18 mu m CMOS technology. The dynamic range of the receiver is increased by incorporating voltage gain controls with wide tuning range at RF and IF stages. For the flicker noise problem, vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are employed as the mixer switching core and at the input stage of the subsequent IF VGA. As a result, this work achieves a 45 dB gain from 5-6 GHz with 6 dB noise floor. The total current consumption is 5.5 mA at 1.8 V supply voltage.
Dynamic Range Reduction Due to RF and Image Signal Co-Existence in a Highly-Merged 2.4/5.7-GHz Dual-Band Low-IF Downconverter
(2010-01-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A highly-merged 2.4/5.7-GHz dual-band low-IF downconverter is demonstrated using 0.18-mu m CMOS technology. Weaver and Hartley architectures are utilized to achieve high image-rejection ratio (IRR) of first and second image signals. The first LO (LO(1)) is set exactly halfway between the two bands. That is, the 2.4/5.7-GHz bands are the first image signal of each other. However, in a real home/commercial environment, a 5.7/2.4-GHz blocking signal is present when the 2.4/5.7-GHz band is desired and degrades the dynamic range of the receiver. Therefore, the dynamic range degradation due to the co-existence of RF and image signals is discussed in this paper.
Comparison on mHEMT Q-Band Sub-Harmonic Mixers With/Without Delay Compensation
(2010)
Syu, Jin-Siang
;
Meng, Chinchun
;
Su, Jen-Yi
;
Huang, Guo-Wei
;
電子工程學系及電子研究所
Q-band sub-harmonic mixers (SHMs) with and without delay compensation are demonstrated in this paper using 0.15-mu m metamorphic high electron mobility transistor (mHEMT) technology. A conventional stacked-LO sub-harmonic mixing cell consists of two Gilbert cells in cascode with quadrature LO inputs. The proposed compensation core in parallel with the stacked-LO core improves the port-to-port isolation. A Marchand balun is employed at the RF port to generate wideband differential signals. As a result, SHMs w/ and w/o compensation achieve the conversion gain of 1/0.5 dB and noise figure of 23/20 dB when 2f(LO)=39/42 GHz. However, the compensation circuit improves the 2LO-to-RF isolation by 12 dB, 2LO-to-IF isolation by 5 dB and RF-to-IF isolation by 5 dB without additional power consumption.
2.4-GHz 7.4-mW 300-kHz Flicker-Noise-Corner Direct Conversion Receiver Using 0.18 mu m CMOS and Deep-N-Well NPN BJT
(2013)
Chang, Wei-Ling
;
Meng, Chin-Chun
;
Syu, Jin-Siang
;
Wang, Chia-Ling
;
Huang, Guo-Wei
A low-power low-flicker-noise receiver is demonstrated using 0.18 mu m CMOS technology. Vertical-NPN bipolar junction transistors (BJTs) in standard CMOS process are used to substitute the mixer switching core and the input stage of subsequent IF VGA. Compared with the conventional CMOS mixer, the excellent flicker noise performance is obtained. As a result, the receiver achieves a 47 dB voltage gain at 2.4-GHz, and the noise figure is 9.6 dB at IF=100 kHz and 5.6 dB for IF>300 kHz. The total current consumption is 4.3 mA at 1.8 V supply voltage.
A 2.4-GHz Low-Flicker-Noise CMOS Sub-Harmonic Receiver
(2013-02-01)
Syu, Jin-Siang
;
Meng, Chinchun
;
Wang, Chia-Ling
;
電機工程學系
;
Department of Electrical and Computer Engineering
A 2.4-GHz low-noise sub-harmonic direct-conversion receiver (SH-DCR) is demonstrated using standard 0.18-mu m CMOS technology. Deep-n-well vertical-NPN (V-NPN) bipolar junction transistors (BJTs) are employed to solve the flicker noise problem in CMOS process. Design optimization of a power-constrained noise-impedance-matched low-noise amplifier (LNA) with the effect of lossy on-chip inductors is fully discussed in this paper. A multi-stage octet-phase polyphase filter is analyzed in detail and implemented to generate well balanced octet-phase LO signals. As a result, the demonstrated receiver achieves 51-dB voltage gain and 3-dB noise figure with flicker noise corner less than 30 kHz when RF = 2.4 GHz. The I/Q amplitude/phase mismatch is below +/-0.2 dB/+/-1 degrees, respectively, covering from 2.35 to 2.6 GHz. The dc current consumption is 5 mA at a 1.8-V supply.

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