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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作,涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.
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Item type:Item, AN OPTIMAL PARALLEL ALGORITHM FOR GENERATING PERMUTATIONS IN MINIMAL CHANGE ORDER(1994-03-01) ;TSAY, JC ;LEE, WP ;資訊工程學系Department of Computer SciencePermutation generation is an important problem in combinatorial computing. In this paper we present an optimal parallel algorithm to generate all N! permutations of N objects. The algorithm is designed to be executed on a very simple computation model that is a linear array with N identical processors. Because of the simplicity and regularity of the processors, the model is very suitable for VLSI implementation. Another advantageous characteristic of this design is that it can generate all the permutations in minimal change order.Item type:Item, DESIGN AND IMPLEMENTATION OF A CHINESE TERMINAL CONTROLLER(1981) ;TSAY, JC ;CHANG, YM ;交大名義發表 ;工學院National Chiao Tung UniversityItem type:Item, A SYSTOLIC GENERATION OF COMBINATIONS(1989) ;LIN, CJ ;TSAY, JC ;應用數學系Department of Applied MathematicsItem type:Item, GENERATING FUNCTION AND EQUIVALENT TRANSFORMATION FOR SYSTOLIC ARRAYS(1989-05-01) ;TSAY, JC ;HOU, YC ;交大名義發表 ;資訊工程學系National Chiao Tung UniversityItem type:Item, A SYSTOLIC DESIGN FOR GENERATING COMBINATIONS IN LEXICOGRAPHIC ORDER(1990-01-01) ;TSAY, JC ;LIN, CJ ;交大名義發表 ;資訊科學與工程研究所National Chiao Tung UniversityItem type:Item, SYSTOLIC FLOW(1990-03-01) ;TSAY, JC ;YUAN, S ;資訊工程學系Department of Computer ScienceItem type:Item, SOME COMBINATORIAL ASPECTS OF PARALLEL ALGORITHM DESIGN FOR MATRIX MULTIPLICATION(1992-03-01) ;TSAY, JC ;SY, Y ;工學院College of EngineeringIn this paper, some combinatorial characteristics of matrix multiplication on regular two-dimensional arrays are studied. From the studies, we are able to design many efficient varieties of the cylindrical array and the two-layered mesh array for matrix multiplication. To design a cylindrical array for matrix multiplication, a systematic design procedure is proposed. In this design procedure, Latin square (a special type of matrix) plays an important role. To design a two-layered mesh array, we find that there is a transformation procedure to transform a cylindrical array to a two-layered mesh array.Item type:Item, ON EQUIVALENT SYSTOLIC DESIGNS OF LU DECOMPOSITION AND ITS ALGEBRAIC REPRESENTATION(1992-12-01) ;HOU, YC ;TSAY, JC ;交大名義發表 ;資訊工程學系National Chiao Tung UniversityAlgorithms which are to be mapped onto interconnecting processing elements in order to design a systolic array are conventionally represented by graphs or networks. This paper introduces the concept of algebraic representation and uses a generating function to represent a systolic array.Item type:Item, ADAPTABLE QUAD TREE TECHNIQUES(1993-07-01) ;SU, SJ ;KUO, YS ;TSAY, JC ;資訊工程學系Department of Computer ScienceThe quad tree is a widely used data structure for region queries. Quad trees normally perform reasonably efficient on the majority of layout data, but could perform very poor on certain extreme data. This demonstrates the quad tree's deficiency in its adaptability to peculiar layout data. We address two aspects of the adaptability problem. On the one hand, the threshold of a quad tree is allowed to change in order to match the global complexity of the layout. On the other hand, a new quad subdivision criterion is developed which adapts a quad tree to the nonuniform distribution of objects with various sizes. Experiments have indicated that the two techniques are indeed useful in coping with the peculiarity of extreme layout data.Item type:Item, A COST-OPTIMAL SYSTOLIC ALGORITHM FOR GENERATING SUBSETS(1994) ;TSAY, JC ;LEE, WP ;交大名義發表 ;工學院National Chiao Tung UniversitySubset generation, generating all 2'' - 1 subsets of an n-element set, is frequently necessary in combinatorial algorithms. In this paper, we shall utilize Moldovan's space-time mapping methodology to design a systolic algorithm for the subset generation problem. The algorithm is a cost-optimal design and can generate all subsets in lexicographic order. Since it can be run on a simple linear systolic array, it is amenable to VLSI implementation.