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Author: search.filters.author.Wang, MFSubject: search.filters.subject.Schottky barrier

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Now showing 1 - 3 of 3
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    Application of field-induced source/drain Schottky metal-oxide-semiconductor to fin-like body field-effect transistor
    (2002-06-01)
    Lin, HC
    ;
    Wang, MF
    ;
    Hou, FJ
    ;
    Liu, JT
    ;
    Huang, TY
    A novel Schottky barrier silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) device was proposed and demonstrated, The new device features a silicide source/drain and field-induced source/drain (S/D) extensions. Excellent ambipolar performance with a near-ideal sub-threshold slope (similar to 60 mV/decade) and high on-/off-state current ratio (comparable to or higher than 10(9)) is realized, for the first time, on a single device. These encouraging results suggest that the new device may be suitable for some niche applications requiring simple and low-temperature processing of complementary metal-oxide-semiconductor(CMOS)-like devices.
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    Ambipolar Schottky barrier silicon-on-insulator metal-oxide-semiconductor transistors
    (2003-02-01)
    Lin, HC
    ;
    Wang, MF
    ;
    Lu, CY
    ;
    Huang, TY
    ;
    電子工程學系及電子研究所
    A novel Schottky barrier silicon-on-insulator metal-oxide-semiconductor field-effect transistor featuring metallic source/drain and an electrical drain junction has been fabricated and characterized. The formation of electrical drain junction, or the field-induced drain (FID), is controlled by a metal field-plate overlying the passivation oxide. Excellent ambipolar operation is demonstrated on the device. Specifically, on/off current ratios up to 10(8) and 10(7) are observed for p- and n-channel operations, respectively. Meanwhile, the off-state leakage current shows very weak dependence on the voltage difference between the main-gate and the drain, highlighting the effectiveness of FID. Finally, negative differential conductance effect is observed for n-channel operation, which is identified as due to dynamic hot electron trapping during device characterization. (C) 2002 Elsevier Science Ltd. All rights reserved.
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    High-performance P-channel Schottky-barrier SOI FinFET featuring self-aligned PtSi source/drain and electrical junctions
    (2003-02-01)
    Lin, HC
    ;
    Wang, MF
    ;
    Hou, FJ
    ;
    Lin, HN
    ;
    Lu, CY
    A simplified and improved Schottky-barrier metal-oxide-semiconductor device featuring a self-aligned offset channel length, PtSi Schottky junction, and reduced oxide thickness underneath the sub-gate was proposed and demonstrated. To alleviate the drawbacks related to the nonself-aligned offset channel length in the original version, a self-aligned offset channel length is achieved in, the new device by forming the silicide source/drain junction self-aligning to the sidewall spacers abutting the gate. This results in not only one mask count saving but also better device performance, as facilitated by, the reduced offset channel length of the self-aligned sidewall spacers. Moreover, the adoption of PtSi for the Schottky junction further improves the on-state current of p-channel operation, while a thinner oxide employed underneath the sub-gate effectively reduces the sub-gate bias needed to form the electrical junction to below 5 V. Significant improvement in on-current as well as leakage current reduction is achieved in the new improved device.