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Now showing 1 - 10 of 18

Use of Random Telegraph Signal as Internal Probe to Study Program/Erase Charge Lateral Spread in a SONOS Flash Memory
(2010)
Chou, Y. L.
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Chiu, J. P.
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Ma, H. C.
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Wang, Tahui
;
Chao, Y. P.
A novel random telegraph signal (RTS) method is proposed to study the lateral spread of injected charges in program/erase of a NOR-type SONOS flash memory. The concept is to use RTS to extract an interface trap position and to detect a local potential variation near the trap due to injection of program/erase charges. By using this method, we find that CHISEL program has a broader charge distribution than CHE program. A mismatch of CHE program electrons and band-to-band erase holes is observed directly from this method.
Statistical Characterization and Modeling of the Temporal Evolutions of Delta V-t Distribution in NBTI Recovery in Nanometer MOSFETs
(2013-03-01)
Chiu, Jung-Piao
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Liu, Yu-Heng
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Hsieh, Hung-Da
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Li, Chi-Wei
;
Chen, Min-Cheng
NBTI trapped charge characteristics and recovery mechanisms are examined by a statistical study of individual trapped charge emissions in nanoscale HfSiON/metal gate pMOSFETs. We measure individual trapped charge emission times in NBTI recovery in a large number of devices. The characteristic time distributions of the first three emitted holes are obtained. The distributions can be well modeled by using a thermally-assisted tunnel (ThAT) detrapping model. NBTI trapped charge energy and spatial distributions and its activation energy distribution in the ThAT model are discussed and extracted. Based on the ThAT model and measured result of single-charge induced V-t shifts, we develop a statistical NBTI recovery Delta V-t evolution model. Our model can well reproduce the temporal evolutions of a Delta V-t distribution in a number of NBTI stressed nanometer MOSFETs in relaxation.
Characterization and modeling of trap number and creation time distributions under negative-bias-temperature stress
(2012-08-20)
Chiu, Jung-Piao
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Li, Chi-Wei
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Wang, Tahui
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電子工程學系及電子研究所
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Department of Electronics Engineering and Institute of Electronics
Individual trapped charge creations and a trap number in p-type metal-oxide-semiconductor field effect transistors (pMOSFETs) under negative bias temperature instability (NBTI) stress are investigated. We find that the characteristic times of a trapped charge creation scatter over several decades of time in small area pMOSFETs, which is attributed to an activation energy distribution in the reaction-diffusion (RD) model of NBTI. We develop a statistical model by combining the RD model with an extracted activation energy distribution to calculate a threshold voltage shift distribution at different NBTI stress times. Our model agrees with measured results very well. (C) 2012 American Institute of Physics. [http://dx.doi.org/10.1063/1.4748108]
Random Telegraph Noise in 1X-nm CMOS Silicide Contacts and a Method to Extract Trap Density
(2012-04-01)
Chen, Min-Cheng
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Lin, Chia-Yi
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Chen, Bo-Yuan
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Lin, Chang-Hsien
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Huang, Guo-Wei
The behavior of random telegraph noise was affected by nickel silicide barrier height engineering in advanced nano-CMOS technologies. Contact resistance fluctuations with magnitude of up to 40% were observed when a Schottky barrier was reduced to 0.2 eV. The large contact resistance instability is attributed to the barrier modification by positive charge trapping and detrapping in a Schottky contact. The prevalence and magnitude of the noise are dependent on the contact area, trap density, trap energy, and the silicide Schottky barrier height. In this letter, we propose a fast method to extract the density of responsible contact traps.
V-t Retention Distribution Tail in a Multitime-Program MLC SONOS Memory Due to a Random-Program-Charge-Induced Current-Path Percolation Effect
(2012-05-01)
Chung, Yueh-Ting
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Huang, Tzu-I
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Li, Chi-Wei
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Chou, You-Liang
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Chiu, Jung-Piao
A V-t retention distribution tail in a multitime-program (MTP) silicon-oxide-nitride-oxide-silicon (SONOS) memory is investigated. We characterize a single-program-charge-loss-induced Delta V-t in NOR-type SONOS multilevel cells (MLCs). Our measurement shows the following: 1) A single-charge-lossinduced Delta V-t exhibits an exponential distribution in magnitudes, which is attributed to a random-program-charge-induced current-path percolation effect, and 2) the standard deviation of the exponential distribution depends on the program-charge density and increases with a program V-t level in an MLC SONOS. In addition, we measure a V-t retention distribution in a 512-Mb MTP SONOS memory and observe a significant V-t retention tail. A numerical V-t retention distribution model including the percolation effect and a Poisson-distribution-based multiple-charge-loss model is developed. Our model agrees with the measured V-t retention distribution in a 512-Mb SONOS well. The observed V-t tail is realized mainly due to the percolation effect.
A Comparative Study of NBTI and RTN Amplitude Distributions in High-kappa Gate Dielectric pMOSFETs
(2012-02-01)
Chiu, J. P.
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Chung, Y. T.
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Wang, Tahui
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Chen, Min-Cheng
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Lu, C. Y.
Random telegraph noise (RTN) and negative bias temperature (NBT) stress-induced threshold voltage (V-t) fluctuations in high-kappa gate dielectric and metal-gate pMOSFETs are investigated. We measured RTN amplitude distributions before and after NBT stress. RTN in poststressed devices exhibits a broader amplitude distribution than the prestress one. In addition, we trace a single trapped charge-induced Delta V-t in NBT stress and find that the average Delta V-t is significantly larger than a Delta V(t)caused by RTN. A 3-D atomistic simulation is performed to compare a single-charge-induced Delta V-t by RTN and NBTI. In our simulation, the probability distribution of a NBT trapped charge in the channel is calculated from the reaction-diffusion model. Our simulation confirms that the NBT-induced Delta V-t indeed has a larger distribution tail than RTN due to a current-path percolation effect.
Investigation of Post-NBT Stress Current Instability Modes in HfSiON Gate Dielectric pMOSFETs by Measurement of Individual Trapped Charge Emissions
(2009)
Ma, H. C.
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Chiu, J. P.
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Tang, C. J.
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Wang, Tahui
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Chang, C. S.
Bipolar charge detrapping induced current instability in HfSiON gate dielectric pMOSFETs after negative bias and temperature stress is studied by using a fast transient measurement technique. Both single electron and single hole emissions are observed, leading to post-stress current degradation and recovery, respectively. The NBT stress voltage and temperature effect on post-stress current evolution is explored. Clear evidence of electron and hole trapping in NBT stress is demonstrated. A bipolar charge trapping/detrapping model and charge detrapping paths based on measured charge emission times are proposed.
Characteristics and physical mechanisms of positive bias and temperature stress-induced drain current degradation in HfSiON nMOSFETs
(2006-06-01)
Chan, Chien-Tai
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Tang, Chun-Jung
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Wang, Tahui
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Wang, Howard C. -H.
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Tang, Denny D.
Drain current degradation in HfSiON gate, dielectric nMOSFETs by positive gate bias and temperature stress is investigated by using a fast transient measurement technique. The degradation exhibits two stages, featuring a different degradation rate and stress temperature dependence. The first-stage degradation is attributed to the charging of preexisting high-k dielectric traps and has a log(t) dependence on stress time, whereas the second-stage degradation is mainly caused by new high-k trap creation. The high-k trap growth rate is characterized by two techniques, namely 1) a recovery transient technique and 2) a charge-pumping technique. Finally, the effect of processing on high-k trap growth is evaluated.
Physics and characterization of various hot-carrier degradation modes in LDMOS by using a three-region charge-pumping technique
(2006-09-01)
Cheng, Chih-Chang
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Lin, J. F.
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Wang, Tahui
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Hsieh, T. H.
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Tzeng, J. T.
Degradation of lateral diffused MOS transistors in various hot-carrier stress modes is investigated. A novel three-region charge-pumping technique is proposed to characterize interface trap (Nit) and bulk oxide charge Q(ox) creation in the channel and in the drift regions separately. The growth rates of N-it and Q(ox) are extracted from the proposed method. A two-dimensional numerical device simulation is performed to gain insight into device degradation characteristics in different stress conditions. This paper shows that a maximum I-g stress causes the largest drain current and subthreshold slope degradation because of both N-it generation in the channel and Q(ox) creation in the bird's beak region. The impact of oxide trap property and location on device electrical characteristics is analyzed from measurement and simulation.
Extraction of nitride trap density from stress induced leakage current in silicon-oxide-nitride-oxide-silicon flash memory
(2006-10-16)
Gu, Shaw-Hung
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Wang, Tahui
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Lu, Wen-Pin
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Ku, Yen-Hui Joseph
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Lu, Chih-Yuan
The authors propose a technique to extract a silicon nitride trap density from stress induced leakage current in a polycrystalline silicon-oxide-nitride-oxide-silicon flash memory cell. An analytical model based on the Frenkel-Poole emission is developed to correlate a nitride trap density with stress induced leakage current. The extracted nitride trap density is 7.0x10(12) cm(-2) eV(-1). They find that nitride trapped charges have a rather uniform distribution in an energy range of measurement (similar to 0.2 eV). (c) 2006 American Institute of Physics.

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