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Design Space Analysis for Cross-Point 1S1MTJ MRAM: Selector-MTJ Cooptimization
(2020-08-01)
Chiang, Hung-Li
;
Chen, Tzu-Chiang
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Song, Ming-Yuan
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Chen, Yu-Sheng
;
Chiu, Jung-Piao
To increase the density of magnetoresistive random accessmemory (MRAM) beyond the 1T1MTJMRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (V-TH-V-HOLD) when the selector is turned on. Also, exponential-type selectorswould degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Omega . mu m(2) and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300-500 mV/decade with the current density similar to 1 MA/cm(2)) and threshold-type selectors (V-TH-V-HOLD similar to 250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%-350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors.
Analytical Modeling of Read-Induced SET-State Conductance Change in a Hafnium-Oxide Resistive Switching Device
(2020-01-01)
Su, Po-Cheng
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Jiang, Cheng-Min
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Chen, Yu-Jia
;
Wang, Chih-Chieh
;
Li, Kai-Shin
A SET-state conductance change in a hafnium-oxide resistive switching memory cell due to repeated read events is investigated. We characterize a read-induced conductance change at different read voltages and SET-state conductance levels. Our result shows that the read-induced conductance degradation exhibits a two-stage evolution with the read pulse number. A SET-state conductance decreases slightly in the first stage and then follows inverse power-law dependence on the read number in the second stage. The power factor is an exponential function of a read voltage without regard to the SET-state conductance level, and the read pulse number at the transition of the two stages is related to a read voltage and conductance level. An analytical model to describe the two-stage conductance evolution is proposed. The parameters in the model are extracted from measurement data. Our model is verified by good agreement between the modeled and measured results in a wide range of read pulse number, read voltage, and SET-state conductance level.
Investigation of Electron and Hole Lateral Migration in Silicon Nitride and Data Pattern Effects on ${V}_{{t}}$ Retention Loss in a Multilevel Charge Trap Flash Memory
(2019-12-01)
Liu, Yu-Heng
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Zhan, Ting-Chien
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Wang, Tahui
;
Tsai, Wen-Jer
;
Lu, Tao-Cheng
We investigate electron and hole lateral migration in retention loss in a multilevel charge trap flash memory. We use hot electron program and band-to-band tunneling hot hole erase to inject various amounts of electrons and holes at the two ends of a SONOS cell. A random telegraph signal (RTS) method is used to distinguish electron and hole lateral movements in silicon nitride. In retention measurement, we apply a voltage to the gate or the source/drain to enhance or retard trapped charge vertical loss and lateral migration. From the evolution characteristics of RTS and traces in retention, we are able to identify the separate roles of electron vertical loss, electron lateral migration, and hole lateral migration in different data patterns. Due to the interaction of stored electrons and holes, we find that retention loss in a program state exhibits a turnaround characteristic as program level increases. loss at low program levels is attributed to hole lateral migration from a neighboring bit. At higher program levels, the influence of hole lateral migration is reduced and loss is dominated by electron vertical loss and lateral migration.
Investigation of Data Pattern Effects on Nitride Charge Lateral Migration in a Charge Trap Flash Memory by Using a Random Telegraph Signal Method
(2018-01-01)
Liu, Y. H.
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Lin, H. Y.
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Jiang, C. M.
;
Wang, Tahui
;
Tsai, W. J.
Data pattern effects on nitride charge lateral migration and V-t retention loss in a charge trap flash memory is investigated. We use channel hot electron program and band-to-band tunneling hot hole erase to inject different amounts of electrons and holes at the two sides of a channel in a SONOS cell. An interface oxide trap near an injected charge packet and its associated random telegraph signal (RTS) are used as an internal probe to detect a local channel potential change resulting from trapped charge lateral migration. Vt retention loss and RTS in various charge storage patterns are characterized and analyzed. At a similar built-in electric field, nitride trapped holes are found to be more mobile than trapped electrons in lateral migration.
Chip-Level Characterization and RTN-Induced Error Mitigation beyond 20nm Floating Gate Flash Memory
(2018-01-01)
Lin, T. W.
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Ku, S. H.
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Cheng, C. H.
;
Lee, C. W.
;
Ijen-Huang
Vt instability caused by random telegraph noise (RTN) in floating gate flash memories beyond 20nm is studied comprehensively. Experiments reveal that the RTN would cause Vt distribution with a kinked tail which re-distributes to a "Gaussian-like" shape rapidly and was measured by the self established Budget Product Tester (BPT). A Multi-Times Verify (MTV) algorithm to mitigate the statistical tail, thus enlarging operation window is also exhibited by BPT. In further, a probability model to portray the compact Vt distribution under MTV is proposed. Finally, the impact of MTV on lowering the requirement of Error-correcting code (ECC) bit is also demonstrated.
Correlation between SET-State Current Level and Read Disturb Failure Time in a Resistive Switching Memory
(2018-01-01)
Su, P. C.
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Jiang, C. M.
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Wang, C. W.
;
Wang, Tahui
;
電子工程學系及電子研究所
The relationship between SET-state current level and read-disturb failure time in a tungsten oxide RRAM is characterized and modeled. Our result shows that read voltage induced reduction of oxygen vacancy density in tungsten oxide follows a power law dependence on cumulative read-disturb time. The power factor is independent of SET-state current level. Read disturb failure time is considerably improved by several orders of magnitude as SET-state current level increases a few times. An analytical model to correlate SET-state current level and read disturb failure time is proposed. Since SET-state current level is related to a cross-section of a conductive filament in an oxide, our model is developed based on a relationship between oxide area and critical oxide trap (oxygen vacancy) density from an oxide breakdown model. The validity of the proposed model is supported by experiment results.
Error Characterization and ECC Usage Relaxation beyond 20nm Floating Gate NAND Flash Memory
(2018-01-01)
Ku, S. H.
;
Lin, T. W.
;
Cheng, C. H.
;
Lee, C. W.
;
Chen, Ti-Wen
Endurance of floating gate flash memories at 19nm node and beyond is studied comprehensively. Experiments reveal that the random telegraph noise (RTN) would degrade the read margin with a tail, which quickly reshapes into a symmetric Gaussian form in a lightly-stressed state. After heavy stress, the lower part of tail would spread further while the upper part keeps roughly overlapped with that during fresh. This unique behavior, which was firstly measured by the self-established Budget Product Tester (BPT), can be explained by stress-induced hole trap creation. To investigate the impact of RTN on operation window, a novel algorithm of Multi-Times-Verify accompanied with the optimal Read-Retry (MTVR2) is proposed and validated by BPT. The advantage of MTVR2 to reduce the requirement of Error-Correcting Code (ECC) bit is demonstrated. Finally, the improvement of bit error rate (BER) in TLC operation with MTVR(2 )is also evaluated.
Analysis and Realization of TLC or even QLC Operation with a High Performance Multi-times Verify Scheme in 3D NAND Flash memory
(2018-01-01)
Lu, C. C.
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Cheng, C. C.
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Chiu, H. P.
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Lin, W. L.
;
Chen, T. W.
Feasibility of multi-times verify (MTV) scheme on triple-level cell (TLC) and quad-level cell (QLC) operations of charge-trap storage 3D NAND memories is investigated comprehensively. Results reveal that random telegraph noise (RTN) and program noise are the major factors affecting lower (LB) and upper boundaries (HB) of Vt distribution, respectively. Enlargement of operation window and reduction of ECC usage with MTV scheme to mitigate RTN-induced LB tail are demonstrated on TLC and QLC operations. In addition, the impact of program noise on HB Vt under various process conditions and ISPP steps is studied experimentally and also explained by our Monte Carlo simulator. Finally, program performance and reserved margin with and without MTV scheme applied on TLC and QLC operation are demonstrated.
Modeling of Read-Disturb-Induced SET-State Current Degradation in a Tungsten Oxide Resistive Switching Memory
(2018-11-01)
Su, Po-Cheng
;
Jiang, Cheng-Min
;
Wang, Chih-Wei
;
Wang, Tahui
;
電子工程學系及電子研究所
We characterize SET-state current degradation induced by read operations in a tungsten oxide resistive memory cell. The current degradation exhibits a two-stage evolution. In the second stage, the current decline follows inverse power-law dependence on cumulative read-disturb time. We present an analytical model to derive the inverse power law. Our model includes oxygen ion activation, mobile oxygen ion hopping, and the reduction of oxygen vacancy density by re-oxidation. Voltage and temperature effects on read-disturb-induced degradation are characterized for comparison with the model. Our results show that the power factor in the inverse power law has exponential dependence on a read voltage.
Variations of V-t Retention Loss in a SONOS Flash Memory Due to a Current-Path Percolation Effect
(2011-04-01)
Chou, Y. L.
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Chung, Y. T.
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Wang, Tahui
;
Ku, S. H.
;
Zou, N. K.
Discrete nitride program charge loss in a small-area SONOS Flash memory cell during retention is observed. Our measurement shows that a retention V-t of a programmed SONOS cell exhibits a stepwise evolution with retention time. Individual single-program charge-loss-induced threshold voltage shifts (Delta V-t) are characterized. We find the following: 1) The magnitude of Delta V-t exhibits an exponential distribution, which is believed due to a current-path percolation effect caused by random program charges and substrate dopants, and 2) program-state V-t retention loss has large variations in different cells and P/E cycles due to the percolation effect. We develop a Monte Carlo analysis to take into account the distribution of Delta V-t and a tunneling front model to study the spread of a retention V-t distribution in a SONOS Flash memory.

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