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Author: search.filters.author.Wu, Chung-YuSubject: search.filters.subject.analog front-end

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    An 1.97 mu W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
    (2018-01-01)
    Chen, Pin-Wen
    ;
    Huang, Chi-Wei
    ;
    Wu, Chung-Yu
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97 mu W per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7 mu V in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85 mu W under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.
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    An 8-Channel Power-Efficient Time-Constant-Enhanced Analog Front-End Amplifier for Neural Signal Acquisition
    (2015)
    Chung, Jung-Chen
    ;
    Chen, Wei-Ming
    ;
    Wu, Chung-Yu
    ;
    電子工程學系及電子研究所
    ;
    生醫電子轉譯研究中心
    In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth of the AFEA is 7 kHz, and the maximum gain is 61.2 dB with power consumption of 1.77 mu W per channel. The TCEA is designed to reduce the high-pass cut-off frequency to 0.16 Hz and achieve a high gain of 50.7 dB with only 4 pF input capacitance. The power consumption of TCEA is 1.08 mu W under 1-V power supply. The noise efficiency factor (NEF) of the TCEA is 2.13 with 4.46 mu V-rms input-referred noise.
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    An 8-Channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS
    (2015)
    Wu, Chung-Yu
    ;
    Ho, Chia-Shiung
    ;
    電子工程學系及電子研究所
    ;
    生醫電子轉譯研究中心
    ;
    Department of Electronics Engineering and Institute of Electronics
    An 8-channel chopper-stabilized analog front-end amplifier (AFEA) is designed in 65-nm CMOS for continuous EEG signal acquisition. The AFEA is composed of eight capacitively coupled chopper instrumentation amplifiers (CCCIAs) with chopper-stabilized circuits and band-pass filters, a multiplexed transconductor, and a transimpedance amplifier. The CCCIA employs an inverter-based folded-cascode amplifier (IBFC) to achieve a better noise-to-power tradeoff and a high gain under 1 V power supply, a DC servo loop to suppress electrode offset and provide a low high-pass corner, a low power ripple reduction loop to suppress chopping ripple, and a positive feedback loop to boost its input impedance. The fabricated AFEA has 59.1/69.8/78 dB programmable gain and 0.81 mu Vrms input-referred noise in a bandwidth of 0.5-100 Hz. The measured power consumption of a single CCCIA is 0.87 mu W. The proposed CCCIA has a lower NEF of 2.97 than other CCCIA for EEG acquisition.