<link rel="stylesheet" href="styles.cf390c6bfbe7555f.css">

學術出版;;Publications

Permanent URI for this communityhdl:11536/1

收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

Browse

🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Wu, Chung-YuSubject: search.filters.subject.electroencephalogram (EEG)

Search Results

Now showing 1 - 3 of 3
  • Thumbnail Image
    Item type:Item,
    A 2.36 mu W/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation
    (2019-01-01)
    Wu, Chung-Yu
    ;
    Huang, Chi-Wei
    ;
    Tsai, Tzung-Lin
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    A 0.18um-CMOS 8-channel EEG acquisition unit with input protection circuits is designed and fabricated for EEG monitoring under the transcranial direct current stimulation (tDCS). The capacitively-coupled chopper instrumentation amplifier (CCCIA) with chopper modulation is used to suppress flicker noise and amplify input EEG signals. To filter out high frequency noise with high linearity, the switched-capacitor low-pass filter (SC-LPF) is proposed. The switchedcapacitor amplifier (SC-Amp) is also proposed to drive ADC capacitor array. The input protection circuit (IPC) is implemented by I/O device to keep internal circuits from overstress and artifacts from the tDCS. A 10-bit SAR ADC with offset-calibration comparator is integrated for accurate ADC conversion. The fabricated EEG acquisition unit has programmable gain 57.5/67.6/78.5dB. The measured power dissipation of a single CCCIA circuit is 2.36 mu W per channel. The measured recovery time is 7.5ms after the tDCS stimulation. It has been verified that the designed chip can record real EEG signals.
  • Thumbnail Image
    Item type:Item,
    An 1.97 mu W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
    (2018-01-01)
    Chen, Pin-Wen
    ;
    Huang, Chi-Wei
    ;
    Wu, Chung-Yu
    ;
    電子工程學系及電子研究所
    ;
    Department of Electronics Engineering and Institute of Electronics
    In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97 mu W per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7 mu V in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85 mu W under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.
  • Thumbnail Image
    Item type:Item,
    An 8-Channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS
    (2015)
    Wu, Chung-Yu
    ;
    Ho, Chia-Shiung
    ;
    電子工程學系及電子研究所
    ;
    生醫電子轉譯研究中心
    ;
    Department of Electronics Engineering and Institute of Electronics
    An 8-channel chopper-stabilized analog front-end amplifier (AFEA) is designed in 65-nm CMOS for continuous EEG signal acquisition. The AFEA is composed of eight capacitively coupled chopper instrumentation amplifiers (CCCIAs) with chopper-stabilized circuits and band-pass filters, a multiplexed transconductor, and a transimpedance amplifier. The CCCIA employs an inverter-based folded-cascode amplifier (IBFC) to achieve a better noise-to-power tradeoff and a high gain under 1 V power supply, a DC servo loop to suppress electrode offset and provide a low high-pass corner, a low power ripple reduction loop to suppress chopping ripple, and a positive feedback loop to boost its input impedance. The fabricated AFEA has 59.1/69.8/78 dB programmable gain and 0.81 mu Vrms input-referred noise in a bandwidth of 0.5-100 Hz. The measured power consumption of a single CCCIA is 0.87 mu W. The proposed CCCIA has a lower NEF of 2.97 than other CCCIA for EEG acquisition.