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A 2.36 mu W/Ch CMOS 8-Channel EEG Acquisition Unit with Input Protection Circuits for Applications Under Transcranial Direct Current Stimulation
(2019-01-01)
Wu, Chung-Yu
;
Huang, Chi-Wei
;
Tsai, Tzung-Lin
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
A 0.18um-CMOS 8-channel EEG acquisition unit with input protection circuits is designed and fabricated for EEG monitoring under the transcranial direct current stimulation (tDCS). The capacitively-coupled chopper instrumentation amplifier (CCCIA) with chopper modulation is used to suppress flicker noise and amplify input EEG signals. To filter out high frequency noise with high linearity, the switched-capacitor low-pass filter (SC-LPF) is proposed. The switchedcapacitor amplifier (SC-Amp) is also proposed to drive ADC capacitor array. The input protection circuit (IPC) is implemented by I/O device to keep internal circuits from overstress and artifacts from the tDCS. A 10-bit SAR ADC with offset-calibration comparator is integrated for accurate ADC conversion. The fabricated EEG acquisition unit has programmable gain 57.5/67.6/78.5dB. The measured power dissipation of a single CCCIA circuit is 2.36 mu W per channel. The measured recovery time is 7.5ms after the tDCS stimulation. It has been verified that the designed chip can record real EEG signals.
A 16-Channel CMOS Chopper-Stabilized Analog Front-End Acquisition Circuits for ECoG Detection
(2017-01-01)
Cheng, Cheng-Hsiang
;
Chen, Zhi-Xin
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a 16-channel analog front-end (AFE) ECoG-signal acquisition circuit for closed-loop seizure control system is presented. It is composed of 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with band-pass filters, 16 programmable transconductance-gain amplifiers, a multiplexer, a transimpedance amplifier, and a 10-bit SAR ADC. The low input-referred noise is achieved by using chopper modulation technique in AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop (ORL) is proposed to reduce output offset generated by input chopper mismatches. The digital ripple reduction loop (RRL) is also used to reduce chopper ripple. Moreover, to prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with high-voltage-tolerant switches is proposed to make the AFE amplifiers sharing the same electrode with high voltage stimulators. The fabricated AFE acquisition circuit has 49.1/59.1/67.9 dB programmable gain and 2.09uV(rms) input referred noise in a bandwidth 0.5-100 Hz. The measured power consumption of AFE is 3.26 uW per channel and the noise efficiency factor (NEF) is 3.78.
An 1.97 mu W/Ch 65nm-CMOS 8-Channel Analog Front-End Acquisition Circuit with Fast-Settling Hybrid DC Servo Loop for EEG Monitoring
(2018-01-01)
Chen, Pin-Wen
;
Huang, Chi-Wei
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
Department of Electronics Engineering and Institute of Electronics
In this paper, a 65nm-CMOS 8-channel Analog Front-End (AFE) acquisition circuit is designed and fabricated for long term EEG monitoring. The Capacitively-Coupled Chopper Instrumentation Amplifier (CCCIA) with chopper modulation is used to amplify input EEG signals and suppress flicker noise. To realize low high-pass corner and large Electrode DC Offset (EDO) rejection ability, a fast-settling Hybrid DC Servo Loop (HDSL) is proposed here. It contains Digital DSL (DDSL) and Analog DSL (ADSL) to achieve better trade-off among power consumption, area, and hardware complexity. An energy-efficient 10-bit SAR ADC with offset-calibration comparator is integrated for accurate A/D conversion. The chip is fabricated in 65nm CMOS technology. The measured overall power dissipation of the acquisition circuit is 1.97 mu W per channel. The input-referred noise of AFE Amplifier (AFEA) is 0.7 mu V in pass band, and the Noise Efficient Factor (NEF) of the CCCIA is 1.99. The measured HDSL calibration time is 125ms. The fabricated SAR ADC has the power consumption of 0.85 mu W under 1V supply and the SNDR of 59.8dB at 100kS/s with the Nyquist input frequency. This chip can record EEG signals successfully and the recorded signal has been verified by NeruScan SynAmps RT 64-channel amplifiers.
A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System
(2018-06-01)
Wu, Chung-Yu
;
Cheng, Cheng-Hsiang
;
Chen, Zhi-Xin
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-todigital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-mu Vrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 mu W per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.
An 8-Channel Power-Efficient Time-Constant-Enhanced Analog Front-End Amplifier for Neural Signal Acquisition
(2015)
Chung, Jung-Chen
;
Chen, Wei-Ming
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth of the AFEA is 7 kHz, and the maximum gain is 61.2 dB with power consumption of 1.77 mu W per channel. The TCEA is designed to reduce the high-pass cut-off frequency to 0.16 Hz and achieve a high gain of 50.7 dB with only 4 pF input capacitance. The power consumption of TCEA is 1.08 mu W under 1-V power supply. The noise efficiency factor (NEF) of the TCEA is 2.13 with 4.46 mu V-rms input-referred noise.
An 8-Channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS
(2015)
Wu, Chung-Yu
;
Ho, Chia-Shiung
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
An 8-channel chopper-stabilized analog front-end amplifier (AFEA) is designed in 65-nm CMOS for continuous EEG signal acquisition. The AFEA is composed of eight capacitively coupled chopper instrumentation amplifiers (CCCIAs) with chopper-stabilized circuits and band-pass filters, a multiplexed transconductor, and a transimpedance amplifier. The CCCIA employs an inverter-based folded-cascode amplifier (IBFC) to achieve a better noise-to-power tradeoff and a high gain under 1 V power supply, a DC servo loop to suppress electrode offset and provide a low high-pass corner, a low power ripple reduction loop to suppress chopping ripple, and a positive feedback loop to boost its input impedance. The fabricated AFEA has 59.1/69.8/78 dB programmable gain and 0.81 mu Vrms input-referred noise in a bandwidth of 0.5-100 Hz. The measured power consumption of a single CCCIA is 0.87 mu W. The proposed CCCIA has a lower NEF of 2.97 than other CCCIA for EEG acquisition.

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