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The Design of CMOS Electrode-Tissue Impedance Measurement Circuit Using Differential Current Switch with CMFB Bias for Implantable Neuro-Modulation SoCs
(2019-01-01)
Huang, Chi-Wei
;
Chung, Chi-Heng
;
Syu, Ruei-Syuan
;
Wu, Chung-Yu
;
交大名義發表
A new electrode-tissue impedance measurement circuit integrated with a System-on-Chip (SoC) is proposed and designed for implantable medical devices to monitor the electrode-tissue contact status. In the proposed circuit, a differential step current is injected into the electrode-tissue structure to generate a voltage. A differential current switch with a common-mode feedback (CMFB) bias circuit and shaped control signals are designed to generate accurate step currents and stable common-mode bias voltage. Moreover, the measurement circuit shares part of the bio-signal acquisition circuit in the SoC. Thus only an extra power dissipation of 4.3 mu W is needed at the operating frequency of 15.625Hz. The proposed circuit is fabricated by 0.18 um CMOS technology. The measurement results have shown that the resolution is 17 Omega(pp) and the maximum error is 3.4% for an impedance of 46k Omega. The proposed circuit is also verified in an in-vitro test by measuring the electrode-tissue impedance of a subdural grid electrode sunk in the phosphate buffered saline (PBS) buffer.
A 16-Channel CMOS Chopper-Stabilized Analog Front-End Acquisition Circuits for ECoG Detection
(2017-01-01)
Cheng, Cheng-Hsiang
;
Chen, Zhi-Xin
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a 16-channel analog front-end (AFE) ECoG-signal acquisition circuit for closed-loop seizure control system is presented. It is composed of 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with band-pass filters, 16 programmable transconductance-gain amplifiers, a multiplexer, a transimpedance amplifier, and a 10-bit SAR ADC. The low input-referred noise is achieved by using chopper modulation technique in AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop (ORL) is proposed to reduce output offset generated by input chopper mismatches. The digital ripple reduction loop (RRL) is also used to reduce chopper ripple. Moreover, to prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with high-voltage-tolerant switches is proposed to make the AFE amplifiers sharing the same electrode with high voltage stimulators. The fabricated AFE acquisition circuit has 49.1/59.1/67.9 dB programmable gain and 2.09uV(rms) input referred noise in a bandwidth 0.5-100 Hz. The measured power consumption of AFE is 3.26 uW per channel and the noise efficiency factor (NEF) is 3.78.
A 16-Channel CMOS Chopper-Stabilized Analog Front-End ECoG Acquisition Circuit for a Closed-Loop Epileptic Seizure Control System
(2018-06-01)
Wu, Chung-Yu
;
Cheng, Cheng-Hsiang
;
Chen, Zhi-Xin
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, a 16-channel analog front-end (AFE) electrocorticography signal acquisition circuit for a closed-loop seizure control system is presented. It is composed of 16 input protection circuits, 16 auto-reset chopper-stabilized capacitive-coupled instrumentation amplifiers (AR-CSCCIA) with bandpass filters, 16 programmable transconductance gain amplifiers, a multiplexer, a transimpedance amplifier, and a 128-kS/s 10-bit delta-modulated successive-approximation-register analog-todigital converter (SAR ADC). In closed-loop seizure control system applications, the stimulator shares the same electrode with the AFE amplifier for effective suppression of epileptic seizures. To prevent from overstress in MOS devices caused by high stimulation voltage, an input protection circuit with a high-voltage-tolerant switch is proposed for the AFE amplifier. Moreover, low input-referred noise is achieved by using the chopper modulation technique in the AR-CSCCIA. To reduce the undesired effects of chopper modulation, an improved offset reduction loop is proposed to reduce the output offset generated by input chopper mismatches. The digital ripple reduction loop is also used to reduce the chopper ripple. The fabricated AFE amplifier has 49.1-/59.4-/67.9-dB programmable gain and 2.02-mu Vrms input referred noise in a bandwidth of 0.59-117 Hz. The measured power consumption of the AFE amplifier is 3.26 mu W per channel, and the noise efficiency factor is 3.36. The in vivo animal test has been successfully performed to verify the functions. It is shown that the proposed AFE acquisition circuit is suitable for implantable closed-loop seizure control systems.
An 8-Channel Power-Efficient Time-Constant-Enhanced Analog Front-End Amplifier for Neural Signal Acquisition
(2015)
Chung, Jung-Chen
;
Chen, Wei-Ming
;
Wu, Chung-Yu
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
In this paper, an 8-channel low-power analog front-end amplifier (AFEA) with time-constant-enhanced topology is proposed for neural signal acquisition. The AFEA is composed of eight time-constant-enhanced amplifiers (TCEAs) and high-pass filters (HPFs), a multiplexed transconductor (MGM) and a transimpedance amplifier (TIA). The AFEA is designed and simulated in 65nm CMOS technology. The bandwidth of the AFEA is 7 kHz, and the maximum gain is 61.2 dB with power consumption of 1.77 mu W per channel. The TCEA is designed to reduce the high-pass cut-off frequency to 0.16 Hz and achieve a high gain of 50.7 dB with only 4 pF input capacitance. The power consumption of TCEA is 1.08 mu W under 1-V power supply. The noise efficiency factor (NEF) of the TCEA is 2.13 with 4.46 mu V-rms input-referred noise.
An 8-Channel Chopper-Stabilized Analog Front-End Amplifier for EEG Acquisition in 65-nm CMOS
(2015)
Wu, Chung-Yu
;
Ho, Chia-Shiung
;
電子工程學系及電子研究所
;
生醫電子轉譯研究中心
;
Department of Electronics Engineering and Institute of Electronics
An 8-channel chopper-stabilized analog front-end amplifier (AFEA) is designed in 65-nm CMOS for continuous EEG signal acquisition. The AFEA is composed of eight capacitively coupled chopper instrumentation amplifiers (CCCIAs) with chopper-stabilized circuits and band-pass filters, a multiplexed transconductor, and a transimpedance amplifier. The CCCIA employs an inverter-based folded-cascode amplifier (IBFC) to achieve a better noise-to-power tradeoff and a high gain under 1 V power supply, a DC servo loop to suppress electrode offset and provide a low high-pass corner, a low power ripple reduction loop to suppress chopping ripple, and a positive feedback loop to boost its input impedance. The fabricated AFEA has 59.1/69.8/78 dB programmable gain and 0.81 mu Vrms input-referred noise in a bandwidth of 0.5-100 Hz. The measured power consumption of a single CCCIA is 0.87 mu W. The proposed CCCIA has a lower NEF of 2.97 than other CCCIA for EEG acquisition.
A 65nm CMOS Low-Power MedRadio-band Integer-N Cascaded Phase-Locked Loop for Implantable Medical Systems
(2014-01-01)
Wang, Yi-Xiao
;
Chen, Wei-Ming
;
Wu, Chung-Yu
;
電機學院
;
College of Electrical and Computer Engineering
This paper presents a low-power MedRadio-band integer-N phase-locked Loop (PLL) system which is composed of two charge-pump PLLs cascade connected. The PLL provides the operation clock and local carrier signals for an implantable medical electronic system. In addition, to avoid the off-chip crystal oscillator, the 13.56 MHz Industrial, Scientific and Medical (ISM) band signal from the wireless power transmission system is adopted as the input reference signal for the PLL. Ring-based voltage controlled oscillators (VCOs) with current control units are adopted to reduce chip area and power dissipation. The proposed cascaded PLL system is designed and implemented in TSMC 65-nm CMOS technology. The measured jitter for 216.96 MHz signal is 12.23 ps and the phase noise is -65.9 dBc/Hz at 100 kHz frequency offset under 402.926 MHz carrier frequency. The measured power dissipations are 66 mu W in the first PLL and 195 mu W in the whole system under 1-V supply voltage. The chip area is 0.1088 mm(2) and no off-chip component is required which is suitable for the integration of the implantable medical electronic system.
A CMOS MedRadio-Band Low-Power Integer-N Cascaded Phase-Locked Loop for Implantable Medical SOCs
(2013)
Liao, Yu-Yu
;
Chen, Wei-Ming
;
Wu, Chung-Yu
;
電機學院
;
College of Electrical and Computer Engineering
In this paper, a low power integer-N cascaded Phase-locked loop (PLL) is proposed to provide the carrier signal and clock signals for a SOC with MedRadio-band transceiver, ADC, DSP, and 13.56-MHz wireless power supply. In the proposed cascaded PLL, the first PLL provides the sampling clocks while the second PLL provides the carrier clock. Furthermore, the 13.56-MHz signal from the receiving coil of the wireless power transmission system is utilized as the input reference signal. Ring-based voltage controlled oscillator (VCO) is designed to minimize both power consumption and chip area. The proposed cascaded PLL is designed and implemented in 0.18-mu m CMOS technology. The measured phase noise is -79 dBc/Hz at 100 kHz offset under 402.9 MHz. The measured power consumptions are 0.28 mW in the first PLL and 0.46mW in the second PLL with a 1.8V supply voltage. The proposed cascaded PLL has low power dissipation, small chip area, and no off-chip components or crystal oscillator. It is suitable for the integration with implantable medical SOCs.

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