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Now showing 1 - 10 of 51

1.7 to 2.3 Gbps OOK LED VLC Transmission Based on 4 x 4 Color-Polarization-Multiplexing at Extremely Low Illumination
(2019-08-01)
Yeh, Chien-Hung
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Weng, Jui-Hung
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Chow, Chi-Wai
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Luo, Chien-Ming
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Xie, Yue-Ru
To achieve the high traffic rate of a GaN LED-based visible light communication (VLC), a 4 x 4 color-polarization-multiplexing system is demonstrated by using two blue and two green LEDs. In the measurement, an available bandwidth of blue and green LEDs can be greater than 465 MHz for VLC modulation traffic by using the suitable analogy front end circuit. Hence, the proposed VLC system can deliver 1.7 to 2.3 Gbit/s ON-OFF keying traffic rates in the free space transmission length of 1-4 m under the extremely low illumination of 6.9-136.1 lux for the indoor application. Moreover, the measured BER of each LED is less than the forward error correction target of 3.8 x 10(-3) to maintain the better signal performance.
Location-controlled-grain Technique for Monolithic 3D BEOL FinFET Circuits
(2018-01-01)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Po-Tsang
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Chen, Kuan-Neng
;
Wu, Wan-Chi
A location-controlled-grain technique is presented for fabricating BEOL monolithic 3D FinFET ICs over SiO2. The grain-boundary free Si FinFETs thus fabricated exhibit steep sub-threshold swing (<70mV/doc.), high driving currents (n-type: 363 mu A/mu m and p-type: 385 mu A/mu m), and high I-on/I-off(>10(6)). According to simulation, the thickness of the interlayer dielectric plays an important role and shall be thicker than 250nm so that the sequential pulse laser crystallization process does not heat the bottom devices and interconnects to more than 400 degrees C.
Complementary inverter circuits based on p-SnO2 and n-In2O3 thin film transistors
(2008-06-09)
Dhananjay
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Chu, Chih-Wei
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Ou, Chun-Wei
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Wu, Meng-Chyi
;
Ho, Zhong-Yo
Thin film transistors (TFTs) of indium oxide (In2O3) and tin oxide (SnO2) were fabricated on SiO2 gate dielectric using reactive evaporation process. Structural investigation of the films revealed that In2O3 films were polycrystalline in nature with preferred (222) orientation and SnO2 films exhibited amorphous nature. The x-ray photoelectric spectroscopy measurements suggest that SnO2 films were oxygen rich and presume mixed oxidation states of Sn, namely Sn2+ and Sn4+. While the In2O3 based TFTs possess n-type channel conduction, SnO2 based TFTs exhibited anomalous p-type conductivity. Integration of these n- and p-type devices resulted in complementary inverter with a gain of 11. (C) 2008 American Institute of Physics.
A promising sputtering route for dense Cu2ZnSnS4 absorber films and their photovoltaic performance
(2014-09-01)
Jheng, Bao-Tang
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Liu, Po-Tsun
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Wu, Meng-Chyi
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光電工程學系
;
顯示科技研究所
Copper zinc tin sulfide (Cu2ZnSnS4, CZTS) is highly abundant in nature. It is an important absorber material for the development of low-cost and sustainable next-generation I-2-II-IV-VI4 thin-film solar cells because it has a the tunable direct band gap energy, inexpensive constituent elements, and a large absorption coefficient in the visible wavelength region. This work develops an efficient one-step vacuum-based approach to depositing CZTS films without the need to supply excess sulfur during/after deposition or to perform any post-sulfurization treatment. This one-step RF sputtering process produces CZTS films that are crystalline, phase-pure, dense, smooth, and continuous. Air Mass 1.5 G power conversion efficiencies of as high as 6% have been achieved with an antireflection coating, demonstrating that this new approach has great potential as a low-cost alternative for high-efficiency CZTS solar cell production. (C) 2014 Elsevier B.V. All rights reserved.
Hybrid TiOx/fluoropolymer bi-layer dielectrics for low-voltage complementary inverters
(2010-01-01)
Sung, Chao-Feng
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Kekuda, Dhananjay
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Chu, Li Fen
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Chen, Fang-Chung
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Cheng, Shiau-Shin
In this article, low temperature processed, reactively evaporated titanium oxide layers were utilized as gate dielectrics for achieving low voltage driven transistors and complementary inverters. The surface of the gate dielectric was modified by an ultra thin (similar to 30 nm) fluoropolymer Cytop (R) layer which partially helped to reduce the leakage in the dielectric films and also enhanced the organic transistor performance. The current investigation demonstrates the ability of these high capacitance bi-layer dielectrics (k similar to 20). The combined p-type and n-type field-effect transistors show similar saturation mobility similar to 0.3 cm(2)/Vs to achieve low voltage driven complementary circuits with output gain of 22. Low temperature processing of these dielectric layers make them easily integrated. (C) 2009 Elsevier B.V. All rights reserved.
Design of Bi-Directional Transmission Gate Driver in Amorphous Silicon Technology for TFT-LCD Application
(2016-01-01)
Zheng, Guang-Ting
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Liu, Po-Tsun
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Wu, Meng-Chyi
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Lu, I-Hsiang
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顯示科技研究所
A novel bi-directional transmission gate driver circuit integrated by amorphous silicon thin film transistors (a-Si: H TFTs) has been proposed. In the proposed design, the noise suppression structure of the gate driver utilized the AC drive inverter to reduce the degradation of the pull down TFTs. The clock frequency of AC signal is 30 Hz, which could reduce dynamic power consumption of the circuit. In addition, the synchronous controlled method in this research could reduce the amount of device in gate driver. The simulated result shows the good output performance of the gate driver and match the circuit design.
Design of dual-outputs-single-stage a-Si:H TFT gate driver for high resolution TFT-LCD application
(2016-05)
Zheng, Guang-Ting
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Liu, Po-Tsun
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Wu, Meng-Chyi
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光電工程學系
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顯示科技研究所
A new gate driver has been designed and fabricated by amorphous silicon technology. With utilizing the concept of sharing the noise free block in a single stage for gate driver, dual-outputs signals could be generated in sequence. By increasing the number of output circuit block in proposed gate driver, number of outputs per stage could also be adding that improves the efficiency for area reduction. Besides, using single driving thin-film-transistor (TFT) for charging and discharging, the area of circuit is also decreased by diminishing the size of pulling down TFT. Moreover, the proposed gate driver has been successfully demonstrated in a 5.5-inch Full HD (1080xRGBx1920) TFT-liquid-crystal display panel and passed reliability tests of the supporting foundry.
Reduced parasitic contact resistance and highly stable operation in a-In-Ga-Zn-O thin-film transistors with microwave treatment
(2016-11-30)
Liu, Po-Tsun
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Chang, Chih-Hsiang
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Zheng, Guang-Ting
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Fuh, Chur-Shyang
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Teng, Li-Feng
In this work, we studied the effects of microwave annealing process on amorphous In-Ga-Zn-O (a-IGZO) thin-film transistors (TFTs) and demonstrated a high performance and reliable device characteristics. The characteristic trapping time (tau) derived from stretched-exponential model was extracted to exhibit the quality improvement of a-IGZO thin film. The microwave annealing features a selective heating and potentially avoids the damage to materials neighboring the a-IGZO channel layer in TFT device structure during thermal processes, resulting in lower parasitic source to drain resistance. (C) 2016 Elsevier B.V. All rights reserved.
The influence of background As on GaSb/GaAs quantum dots and its application in infrared photodetectors
(2012)
Lin, Wei-Hsun
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Tseng, Chi-Che
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Wu, Shung-Yi
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Wu, Meng-Hsun
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Lin, Shih-Yen
In this paper, GaSb nanostructures prepared under different Sb/background As ratios are investigated. With decreasing Sb/background As ratios, the morphologies of GaSb nanostructure changing from quantum dots (QDs) to quantum rings (QRs) are observed. The higher optical recombination probabilities of GaSb QRs are attributed to enhanced electron-hole wave function overlapping and more surrounding electrons around the GaSb QR core shell. With well-control Sb/background As ratios, the high-temperature operation GaSb quantum-dot infrared photodetector (QDIP) with simple stacked structure has been demonstrated. (C) 2011 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim
Logic/Memory Hybrid 3D Sequentially Integrated Circuit Using Low Thermal Budget Laser Process
(2015)
Yang, Chih-Chao
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Hsieh, Tung-Ying
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Huang, Wen-Hsien
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Wu, Tsung-Ta
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Wang, Hsing-Hsiang
High performance 3D sequentially stackable nanowire FETs and non-volatile memories (NVMs) with threshold voltage engineering and driving current boosting technologies were demonstrated by using low thermal budget nanosecond laser crystallization and laser activation technologies. The local heating laser process without damaging the underlying device/circuit realizes the across -layer and in -layer integration of high-speed 3ps logic circuits and 1-T 100ns plasma-MONOS NVMs as well as low driving-voltage 6T SRAMs with static noise margin (SNM) of 280 mV. Such logic/memory hybrid 3D sequentially integrated circuit provides power efficient computing and storage. Moreover, the monolithically stacking of Si thin-film energy harvester envisions lower power and low cost 3D(+)IC for internet of things.

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