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收集所有交通大學研究人員與學生個人或團體所發表之各項學術著作，涵蓋期刊論文、教師專書、學位論文等項。;;Collections of Publications of NCTU Researchers and Students Like Journal Papers and Thesis.

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🏛️國立陽明交通大學機構典藏

Author: search.filters.author.Yen, Cheng-ChengHas files: No

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Now showing 1 - 7 of 7
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    Protection Design Against System-Level ESD Transient Disturbance on Display Panels
    (2010-01-01)
    Ker, Ming-Dou
    ;
    Lin, Wan-Yen
    ;
    Yen, Cheng-Cheng
    ;
    Yang, Che-Ming
    ;
    Chen, Tung-Yang
    A hardware/firmware system co-design has been proposed in this work to protect display electronic products against system-level electrostatic discharge (ESD) transient disturbance. By including transient detection circuit, the firmware can execute system recovery procedure to recover all electrical functions under system-level ESD tests. The transient detection circuit is designed to detect different positive and negative fast electrical transients and verified in a 0.13 mu m CMOS process. The experimental results have confirmed that the proposed hardware/firmware design can successfully improve the susceptibility of display products against system level ESD zapping.
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    Transient-to-Digital Converter for Protection Design in CMOS Integrated Circuits against Electrical Fast Transient
    (2009)
    Yen, Cheng-Cheng
    ;
    Ker, Ming-Dou
    ;
    Liao, Chi-Sheng
    ;
    Chen, Tung-Yang
    ;
    Tsai, Chih-Chung
    An on-chip transient-to-digital converter for protection design against electrical fast transient (EFT) is proposed. The proposed transient-to-digital converter is designed to detect fast electrical transients under EFT tests. The output digital codes can correspond to different EFT voltages during the EFT-induced transient disturbances. The experimental results in a 0.18-mu m CMOS integrated circuit (IC) with 3.3-V devices have confirmed the detection function and digital output codes.
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    Latchup-like failure of power-rail ESD clamp circuits in CMOS integrated circuits under system-level ESD test
    (2007)
    Ker, Ming-Dou
    ;
    Yen, Cheng-Cheng
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    Two different on-chip power-rail electrostatic discharge (EaD) protection circuits, (1) with NMOS and PMOS feedback, and (2) with cascaded PMOS feedback have been designed and fabricated in a 0.18-mu m CMOS technology to investigate their susceptibility to system-level ESD test. The main purpose for adopting the feedback loop into the power-rail ESD clamp circuits is to avoid the false triggering during a fast power-up operation. However, during the system-level ESD test, where the ICs in a microelectronics system have been powered up, the feedback loop used in the power-rail ESD clamp circuit provides the lock function to keep the main ESD device in a "latch-on" state. The latch-on ESD device, which is often designed with a larger device dimension to sustain high ESD level, conducts a huge current between the power lines to perform a latchup-like failure after the system-level ESD test. The susceptibility of power-rail ESD clamp circuits with the additional board-level noise filter to the system-level ESD test is also investigated. To meet high system-level ESD specifications, the chip-level ESD protection design should be considered with the transient noise during system-level ESD stress.
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    Transient-induced latchup in CMOS integrated circuits due to electrical fast transient (EFT) test
    (2007)
    Yen, Cheng-Cheng
    ;
    Ker, Ming-Dou
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    The transient-induced latchup (TLU) in CMOS ICs under electrical fast transient (EFT) test has been investigated by experimental verification. With positive and negative voltage pulses under EFT test, the TLU can be triggered on in CMOS ICs with the parasitic pnpn structure. The physical mechanism of TLU in CMOS ICs has been developed with experimental verification in time domain. All the experimental evaluations have been verified with the silicon-controlled rectifier (SCR) test structure fabricated in a 0.18-mu m CMOS technology.
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    Unexpected failure in power-rail ESD clamp circuits of CMOS integrated circuits in microelectronics systems during electrical fast transient (EFT) test and the re-design solution
    (2007)
    Ker, Ming-Dou
    ;
    Yen, Cheng-Cheng
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    Four different on-chip power-rail electrostatic discharge (ESD) clamp circuits have been designed to investigate their susceptibility to electrical fast transient (EFT) test. From the experimental results, the feedback loop in two kinds of on-chip power-rail ESD clamp circuits provides the lock function to perform a latchup-like failure after the EFT test. The re-design solution will be developed to overcome this issue to meet the regulation of EFT/EMC test.
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    Transient Detection Circuit for System-Level ESD Protection and Its On-Board Behavior with EMI/EMC Filters
    (2008)
    Ker, Ming-Dou
    ;
    Liao, Chi-Sheng
    ;
    Yen, Cheng-Cheng
    ;
    電機學院
    ;
    College of Electrical and Computer Engineering
    A new on-chip transient detection circuit for system-level electrostatic discharge (ESD) protection is proposed. The circuit performance of detecting fast electrical transients has been verified in a 0.18-mu m CMOS integrated circuit (IC). The experimental results have confirmed that the proposed on-chip transient detection circuit can detect positive and negative fast electrical transients during system-level ESD zapping. Three board-level noise filtering networks have been investigated their enhancement on detection range of the proposed on-chip transient detection circuit. The chip-level solution can be further co-designed with the board-level solution in order to meet high system-level ESD specification.
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    Transient-to-Digital Converter for ESD Protection Design in Microelectronic Systems
    (2008)
    Ker, Ming-Dou
    ;
    Yen, Cheng-Cheng
    ;
    Liao, Chi-Sheng
    ;
    Chen, Tung-Yang
    ;
    Tsai, Chih-Chung
    An on-chip transient-to-digital converter for system-level electrostatic discharge (ESD) protection is proposed. The proposed transient-to-digital converter is designed to detect fast electrical transients during the system-level ESD events. The output digital thermometer codes can correspond to different ESD voltages under system-level ESD tests. The experimental results in a 0.18-mu m CMOS integrated circuit (IC) with 3.3-V devices have confirmed the detection function and digital output codes.